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    1,850 anloge vhdl công việc được tìm thấy, giá USD

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $305 (Avg Bid)
    $305 Giá đặt trung bình
    5 lượt đặt giá

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $221 (Avg Bid)
    $221 Giá đặt trung bình
    8 lượt đặt giá

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
    $33 / hr Giá đặt trung bình
    1 lượt đặt giá

    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

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    Need example code de-10 Đã kết thúc left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    More details will be shared via chat

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    9 lượt đặt giá

    More details will be shared via chat

    $18 (Avg Bid)
    $18 Giá đặt trung bình
    8 lượt đặt giá

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $80 (Avg Bid)
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    Complex Signal Mixer VHDL Đã kết thúc left

    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

    $102 (Avg Bid)
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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    Project for Jin Q. Đã kết thúc left

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

    $30 (Avg Bid)
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    Project for Nick B. Đã kết thúc left

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

    $30 (Avg Bid)
    $30 Giá đặt trung bình
    1 lượt đặt giá
    Project for Jin C. Đã kết thúc left

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

    $30 (Avg Bid)
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    1 lượt đặt giá
    Temperature sensor and FPGA Đã kết thúc left

    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    FPGA and Vhdl expert needed Đã kết thúc left

    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    Wanted Online FPGA Tutor Đã kết thúc left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    FPGA Development Đã kết thúc left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

    $57 / hr (Avg Bid)
    $57 / hr Giá đặt trung bình
    20 lượt đặt giá
    Filtro de 3 bandas en vhdl Đã kết thúc left

    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Counter in VHDL Đã kết thúc left

    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

    $30 (Avg Bid)
    $30 Giá đặt trung bình
    1 lượt đặt giá

    Implementation of Fractional order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please.

    $168 (Avg Bid)
    $168 Giá đặt trung bình
    3 lượt đặt giá

    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

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    4-bit vhdl divider Đã kết thúc left

    It is required to design a 4-bit binary divider. The division can be limited to un-signed numbers only. Feel free to implement the divider by any architecture you like, but be sure to understand and be able to verify the operation of the selected architecture. Fig. 1 shows a binary division example to recap the binary division process. -Structural and behavioral codes for the binary divider using...

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    Add uart to MIPS Đã kết thúc left

    I Have mips in VHDL code, I want to add to it UART

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    help running mips on FPGA Đã kết thúc left

    I got MIPS in VHDL, but when I run it on FPGA, It seems to do nothing, although it's working in simulation.

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    Dice game in VHDL for board Đã kết thúc left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [đăng nhập để xem URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [đ...

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    Wristwatch-VHDL -- Vivado Đã kết thúc left

    Design a multifunction wristwatch that has time-keeping, alarm, and stopwatch functions. The wristwatch has three buttons (B1, B2, and B3) that are used to change the mode, set the time, set the alarm, start and stop the stopwatch, and so on. Pushing button B1 changes the mode from Time to Alarm to Stopwatch and back to Time. The functions of other buttons vary depending on the mode.

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    Design principle (VHDL) Đã kết thúc left

    RTL design project All of the data required to explain what I want are found in the attached file

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    Dice game VHDL Đã kết thúc left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [đăng nhập để xem URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [đ...

    $8 (Avg Bid)
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    VHDL project Đã kết thúc left

    Anyone who is good in VHDL and can help me in implementing load, move, add, xor

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    Design a circuit that emulates an alarm system, which is armed and disarmed with a code consisting of 4 symbols given by the buttons on the board (for example btnC, btnL, btnR, btnU). The alarm is armed or disarmed when the correct code combination is entered. When the alarm is disarmed, LED0 is on, when the alarm is armed, LED15 is on. SW0 is a sensor, when the alarm is armed and SW0 = 1, the LED...

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    VHDL project Đã kết thúc left

    I need a vhdl project that integrates IoT and communications.

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    DICE GAME in VhDL Đã kết thúc left

    Design an electronic dice game (Craps in the United States). The game involves two dice, each of which can have a value between 1 and [đăng nhập để xem URL] counters are used to simulate the roll of the dice. Each counter counts in the sequence 1, 2, 3, 4, 5, 6, 1, 2,… Thus, after the “roll” of the dice, the sum of the values in the two counters will be in the range 2 through [đ...

    $78 (Avg Bid)
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    6 lượt đặt giá

    I need single cycle 32 bit mips vhdl coding to find prime numbers. I will provide code to find prime number so you just have to build cpu for this specific purpose and I am also going to provide parameters for this architecture. I am gonna share project file after finalising with best person to do this job

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    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and test...

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    I'm a electronic engineer and I have a good command on computer programs and also on digital programming like VHDL.

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    You have to write code and report for this .

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    I have the scheme of the project need only to work with the basys 3. Only to use buttons and switches from the basys3. Need the whole code in VHDL for Vivado.

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    Develop a 32‐bit single or multi‐cycle CPU capable of performing a search for prime numbers.    CPU

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    Create VHDL chess clock Đã kết thúc left

    Has to be completed by the end of tomorrow (13/05/2019) Create VHDL code for chess clock, uploaded the task as a file.

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    Some work related to fpga and vhdl. Need any expert who can manage that

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    I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [đăng nhập để xem URL] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with this alforithm. You can modify input...

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    Nexys 4 Artix-7 Accelerometer Đã kết thúc left

    Want to be able to use accelerometer data on microblaze softcore processor, need SPI driver and interface on VHDL

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    Hi, We have to make a report & VHDL coding with simulation. Please bid who are expert from an electrical engineering background. After that, we would discuss more details. Please give your best quote & we would make long term relationship with the perfect electrical engineering freelancer. Thanks.

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