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    3,385 e1 vhdl công việc được tìm thấy, giá theo USD

    Tôi cần xúc tiến thương mại cho sàn CLoan - Sàn kết nối người đi vay và cho vay thế chấp bằng tài sản số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi khảo sát người đi vay :[đăng...

    $21 (Avg Bid)
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    Hiện tại mình đang cần người tiếp tục phát truyện cổng truyện online của trang VipTruyen.Vn. Nếu bạn chuyên về php hãy tham gia dự án của bọn mình. Giá hoàn thành website là 3 triệu đến 5 triệu. Nếu các bạn muốn tham gia vào dự án của mình thì sẽ thảo luận thêm. Yêu cầu của m...

    $138 (Avg Bid)
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    7 lượt đặt giá

    Hiện tại bên mình đang chạy cho dự án sắp tới nên cần tuyển gấp 1 số freelancer về Apk iOS, Android, không phải game và design. Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghiệm, hợp tác lâu dài nhiều d...

    $991 (Avg Bid)
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    Hey, I am Muhammad Javed from Pakistan, Basically I am developing a team of engineers in all domains of electrical engineering. I have lot of clients and lot of projects but don't have professionals to manage them. I am finding experts in following areas: -->> VHDL/Verilog FPGA -->> Raspberry Pi -->> Arduino/ESP32 -->> Linux OS -->> PCB Design + Prototyp...

    $463 (Avg Bid)
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    entry level VHDL projects 1) Design of a Combinational Barrel Shifter/Rotator 2) Division by Constant 3) serial adder 4) FSM Design – Digital Lock 5) memory block copy will not pay above 20$ for each assignment. so quote me accordingly. will pay fixed rate per assignment. will not allow tardiness.

    $43 (Avg Bid)
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    Looking for VHDL expert. I will share details via chat. Thank

    $53 (Avg Bid)
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    I am looking for VHDL Developer 3 ngày left
    ĐÃ XÁC THỰC

    I am looking for VHDL Developer Count and output the number of 1’s in a parallel 8-bit input Design and simulate a BCD counter whose initial count is 5

    $23 (Avg Bid)
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    Need help with these two problems and the report after, Report, screenshots, testbench, correct solutions

    $46 (Avg Bid)
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    I would like that my Fixmebus environment (RS485 based system with 1 master and many slaves) be on the ESP Home homepage ! You will be responsible to write a Python code on a PI4B+ hardware to be able to discuss with all my Fixmebus slaves (relays, sensors, etc.).... You'll need to install Moxa Miineport E1 COM over LAN drivers on the PI, and then talk on the Fixmebus and exchange messages wi...

    $560 (Avg Bid)
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    I am looking for electrical engineers having good expertise in following FPGA Xilinx Verilog/VHDL Raspberry Pi ESP32/Arduino

    $153 (Avg Bid)
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    16 lượt đặt giá

    VHDL Half adder using two processes, 1-bit Full-Adder using Half adder as a component, using port map N=4 bit adder using 1-bit Full Adder as a component. Design N-bit add-sub unit using behavioral VHDL model

    $30 (Avg Bid)
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    VHDL Half adder using two processes, 1-bit Full-Adder using Half adder as a component, using port map N=4 bit adder using 1-bit Full Adder as a component. Design N-bit add-sub unit using behavioral VHDL model

    $83 (Avg Bid)
    $83 Giá đặt trung bình
    3 lượt đặt giá
    Quartus Altera/INTEL Đã kết thúc left

    Looking for a tutor on Quartus Altera/Intel MAX10 FPGA device. Knowledge of QSYS, Platform designer, Eclipse, HDL/VHDL. Embedded system control design using FPGA. Closed loop control ADC sampling, PI controller , PWM generation in HDL/VHDL.

    $12 / hr (Avg Bid)
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    Looking for website content for Power electronics converter for battery chargers for EV market. Magnetics design , Embedded software FPGA. Altera/Intel VHDL.

    $15 / hr (Avg Bid)
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    VHDL project Đã kết thúc left

    I need small help in VHDL project

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    Need to integrate existing Mitel (md-one) pabx with a new Pabx via E1. Basic call functionalities (caller name / number / forwarding and hold features) between two pabxs should present after integration.

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    The circuit must follow the below specifications: Adder must be implemented using carry look ahead architecture Multiplier must be implemented from scratch from a hardware point of view Carefully choose the size for the adder and the registers used in the circuit and show how did you estimate the size To be delivered: 1. Report: Block diagram for the adder and multiplier State diagram for the ...

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    Code For Me Đã kết thúc left

    All i need in this project is Block diagram for the adder and multiplier , State diagram for the FSM , Code added as appendix with detailed description for each part , All VHDL files used and Test bench code.

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    Finite State Machine project Đã kết thúc left

    Report writing and a code using VHDL

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    Design Pedometer using VHDL Đã kết thúc left

    Write VHDL code and write a report for Pedometer

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    Trophy icon Design my new opening store leaflet Đã kết thúc left

    Supergrows Cosmetics is a professional Hair, Nail and Beauty Supplier. We are opening a new store in Tower Hamlets and will be distributing our leaflets throughout the borough to over 150,000 people. We need to let the population of the borough of Tower Hamlets know WHAT we are, WHO we are, and WHERE we are. I have included photos of our previous campain in September 2020, when we opened a ne...

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    - a VHDL programme All the task related to the VHDL only. Rest will share in requirements

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    You are required to implement a Multiplier Accumulator Circuit (MAC). This circuit takes two sets of 10 inputs; each input is 8 bits long. The circuit multiplies the each two corresponding numbers in the set and adds the results to the following number and so on. After all the results for the entire set is calculated, the output register produces the output of the circuit and the operation is repe...

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    VHDL SD card implementation Đã kết thúc left

    Hello, In my project I need to store data on my FPGA Altera EVMs. The data must be stored on a non-volatile device (power done can occur at all time). To do that, I need to implement an interface to the on board uSD card. Here are some specification: 1. SD Card: Class 10, 2GB. 2. Min write speed: 200Byte every 1ms (effective) ~1.6Mbps. 3. Read speed: 10Mbps (Flash all mode) 4. All VHDL (NiosI...

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    FPGA data capture Đã kết thúc left

    Want to see real time FPGA data in matlab using FPGA data capture with VHDL code.

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    VHDL Hash program Đã kết thúc left

    I need FPGA program developed in VHDL, i have this code in C# but i need to run it in FPGA to get better performance. ### PSEUDOCODE ### CipherData = 0x123 InitialVector = 0x123 Salt = 0x123 Rounds = 30000 TestData = "Hello world" <- It can be byte array input AesKey = OpenSSL_derivation(TestData, Salt) loop (0 to Rounds) { AesKey = SHA512(AesKey) } if( [đăng nhập để xem URL](...

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    Project for Amal A. Đã kết thúc left

    Hi Amal A., Same e1 project. Synway card. I have live ip now

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    For this project, we are looking for an RTL developer to assist in developing a technology Proof of Concept for a simplified FPGA-based system to store data in non-volatile memory (NVMe SSDs). Key Technologies you should be comfortable with are VHDL/Verilog, Xilinx FPGAs, Ethernet, NMVe, and RDMA/RoCE, IEEE 754 FPU, ARM Cortex-M1, and Xilinx Linux (Rustlang, Python, and Apache Arrow are also desi...

    $1276 (Avg Bid)
    $1276 Giá đặt trung bình
    13 lượt đặt giá

    For this project, we are looking for an RTL developer to assist in developing a technology Proof of Concept for a simplified FPGA-based system to store data in non-volatile memory (NVMe SSDs). Key Technologies you should be comfortable with are VHDL/Verilog, Xilinx FPGAs, Ethernet, NMVe, and RDMA/RoCE, IEEE 754 FPU, ARM Cortex-M1, and Xilinx Linux (Rustlang, Python, and Apache Arrow are also desi...

    $620 (Avg Bid)
    $620 Giá đặt trung bình
    9 lượt đặt giá

    For this project, we are looking for an RTL developer to assist in developing a technology Proof of Concept for a simplified FPGA-based system to store data in non-volatile memory (NVMe SSDs). Key Technologies you should be comfortable with are VHDL/Verilog, Xilinx FPGAs, Ethernet, NMVe, and RDMA/RoCE, IEEE 754 FPU, ARM Cortex-M1, and Xilinx Linux (Rustlang, Python, and Apache Arrow are also desi...

    $564 (Avg Bid)
    $564 Giá đặt trung bình
    9 lượt đặt giá
    Walk error module Đã kết thúc left

    The project needs the module of walk error for TOF sensor. The module should be design in vhdl

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    This is a Penn Foster project. Prepare a partial set of structural drawings using AutoCAD. Drafting the First Floor Framing Plan (Sheet 1). Drafting the South Elevation (Sheet 2). Drafting Section A (Sheet 3. Drafting Section B (Sheet 4). Drafting Details C, C1, and C2 (Sheet 5).Drafting Connection Details D, D1, F, and F1 (Sheet 6). Drafting Foundation Details E and E1 (Sheet 7). For someone tha...

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    FPGA/VHDL Task Đã kết thúc left

    Title: Design and Implementation of an ’16-bit Reduced Instruction Set computer (RISC) system for Robot Applications’ Design Problem specification: To design and implement a robotic system, RISC processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit RISC processor for the given instruction set in VHDL. You are req...

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    Need a VHDL Expert Đã kết thúc left

    Title: Design and Implementation of an ’16-bit Reduced Instruction Set computer (RISC) system for Robot Applications’ Design Problem specification: To design and implement a robotic system, RISC processors are considered vital as they provide security and reliability. You are required to program and demonstrate a 16-bit RISC processor for the given instruction set in VHDL. You are ...

    $48 (Avg Bid)
    $48 Giá đặt trung bình
    5 lượt đặt giá
    VHDl Based design Đã kết thúc left

    ADS7038 Xilinx Virtex DAC7750 If 1Vpp is given to ADS7038 it should convert that input into digital signal and store it into the memory of Xilinx Virtex FPGA and DAC7750 should convert the digital stored data into analog 1Vpp. Write VHDL code for communication with ADS7038 and DAC7750 where FPGA Virtex is the master controller. Write the code on Xilinx Vivado and send simulation pictures. The c...

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    7 lượt đặt giá

    Modulation and Demodulation of QPSK using VHDL using XILINX IDE.

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    Code a VHDL program Đã kết thúc left

    enable to design and implement a complex digital circuit using VHDL.

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    Outbound IVR Dialer Solution Đã kết thúc left

    The project involves creating an outbound dialer software with IVR functionality.: • Develop a system that is capable of making bulk calls to recipients. • The system must be able to be hosted online and be able to connect to operator E1/SIP Trunk. • The system must be able to schedule phone calls. The system must have a phone book, that includes name, number and sex (male or femal...

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    Trophy icon Looking for a Logo Đã kết thúc left

    Need a logo for my business incorporating this image, it's called "E1 Archery Products"

    $18 (Avg Bid)
    Bảo đảm
    $18
    106 bài tham dự
    Vhdl designer Đã kết thúc left

    I am using HI 8429 IC to to convert discrete to digital. I have to implement this module using vhdl along with bfm.i am adding data sheet along with this message.

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    Design an ALU Đã kết thúc left

    Design an ALU that implements the MIPS instructions using specific components. VHDL code is necessary.

    $38 (Avg Bid)
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    I need help making ALU in Quartus Prime using VHDL.

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    VHDL DESIGNER Đã kết thúc left

    • All the coursework has to be done in VHDL. Coursework handed in using another language will be marked as zero. • Coursework must be typeset. • Never use screenshots or photograph of code in your coursework. Typeset code within your coursework report using a monospace font (e.g. courier new). • Never use photographs of waveforms in your coursework. Use a proper screen capture ...

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    I Need a VHDL Coder. Đã kết thúc left

    I Need a VHDL Coder. Digital Design

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    VHDL in Quartus and testbench in Modelsim for business purpose VHDL half adder VHDL full adder

    $72 (Avg Bid)
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    vhdl,fpga and CAO project Đã kết thúc left

    I need some one very good in vhdl,fpga and CAO for a project

    $70 (Avg Bid)
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    vhdl design Đã kết thúc left

    designing a finite state machine with corresponding logics of the testbench and design, the following relational project will be given to you thus, giving a hint of how the project is.

    $27 / hr (Avg Bid)
    $27 / hr Giá đặt trung bình
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    Help with vhdl coding Đã kết thúc left

    need help solving a few vhdl coding problems

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    need help with VHDL coding using Quartus prime and modelsim

    $20 (Avg Bid)
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    8 lượt đặt giá