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    3,595 e1 vhdl công việc được tìm thấy, giá theo USD

    Tôi cần xúc tiến thương mại cho sàn CLoan - Sàn kết nối người đi vay và cho vay thế chấp bằng tài sản số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi...số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi khảo sát người đi vay : người kiếm tiền: Những người hoàn thành khảo sát và để lại thông tin cá nhân sẽ được nhận phần quà trị giá 10$ tại Clo...

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    Hiện tại mình đang cần người tiếp tục phát truyện cổng truyện online củ...hãy tham gia dự án của bọn mình. Giá hoàn thành website là 3 triệu đến 5 triệu. Nếu các bạn muốn tham gia vào dự án của mình thì sẽ thảo luận thêm. Yêu cầu của mình là các bạn tiến hành sửa chữa và nâng cấp cổng truyện theo yêu cầu của mình. Các bạn tải bản phác thảo của mình tại: %A3n+Th%E1%BA%A3o+Thi%E1%BA%BFt+K%E1%BA%BF+C%E1%BB%95ng+Truy%E1%BB%87n+Ho%C3%A0n+Ho%C3%A0n+Ch%E1%BB%89nhVipTruyen+%283% Mình đang ở Sài Gòn, nên muốn làm việc với những người...

    $138 (Avg Bid)
    $138 Giá đặt trung bình
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    Hiện tại bên mình đang chạy cho dự án sắp tới nên cần tuyển gấp 1 số freelancer về Apk iOS, Android, không phải game và design. Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghi...Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghiệm, hợp tác lâu dài nhiều dự án. Các bạn có thể giới thiệu bạn bè tham gia nhóm outsource này. Budget chi phí cho phần outsource không cố định, phụ thuộc vào module nhận thầu....

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    Calling out for experienced UI/UX Web Designer who can use his/her expertise in designing the most apposite website for the purpose. Idea: To build a 4-5 pager website targeting the most affluent discerning HNI's from around the world looking for luxury concierge services including uber luxury travel experiences, Privat...It must be drool worthy, must justify distinct luxury from font size to colour schemes and minuscule of details that speaks for itself. Project Requirement: Web and Logo Design Reference websites for design ideas and inspiration:

    $523 (Avg Bid)
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    VHDL test procedure and test bench implementation

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    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

    $358 (Avg Bid)
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    VHDL designer 1 giờ left

    ARINC429 frame decoding on Xilinx spartan 6 or 7 FPGA based platform

    $354 (Avg Bid)
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    Need to convert MATLAB code to synthesizable VHDL code. I am using DE2 FPGA board for testing

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    8 bit counter and BCD counter Đã kết thúc left

    -Write a VHDL file for an 8-bit counter with active-LOW asynchronous clear, active-HIGH synchronous load, active-HIGH count enable, and a directional input that makes the circuit count up when DIRECTION = 1 and down when DIRECTION = 0. - Write a set of simulation criteria that verifies the operation of the counter. The simulation must contain one complete cycle of the counter and test all functions. It must show that the synchronous load really is synchronous and that the clear has precedence over load, which in turn has precedence over count enable. -Write a VHDL file for a two-digit BCD counter with active-LOW asynchronous clear, active- HIGH synchronous load, and an active-HIGH count enable. -The counter must count up from 00 to 09, then 10 to 19, and so on until it reache...

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    Animation with 5 actions : Character has front-view layout as the given file (GIF format and AI format) (please inbox for character 2D front image) Idle (same for 5 ...Moving and attack like this : 3- 2 pistol man (inclue bullets flying) Moving and attack like this : 4- Riffle man (sniper - inclue bullet flying) Moving and attack like this : 5- Staff man (inclue a fireball attack) Moving and attack like this : OUR budget is 375$ for 5 characters (75$ each one)

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    Need to Convert MATLAB code to VHDL code. I Have a MATLAB code i want someone who can convert that code to a sytnthesizable VHDL code for ALtera FPGA.

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    Project for Sardar Hasnain A. Đã kết thúc left

    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    Project for Damian L. Đã kết thúc left

    I will love to chat with you about my project. Please let me know when you can https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details

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    Project for Loganathan N. Đã kết thúc left

    I have a project i want to talk to you about https://www.freelancer.com/projects/verilog-vhdl/FPGA-expert-34634495/details Please let me know when you have time to chat

    $10 (Avg Bid)
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    photoshop and GIF design Đã kết thúc left

    We need GIF images to start minting NFTs Size should be 350x350 Its about cartoon character 5 characters in total - Sword and shield - Bow - Gun - Spear - Staff Example : We need this style but dont want a 100% copy from them It could be a dickhead character :) kind of ^^ Animated should be like the 0:13 to 0:46 of video (a verry simple animated) Our budget is 40$ / character (total budget for project is 200$) Each character should be delivered in photoshop and Gif 5 colors for each type. Please bid correct amount or lower if you want to get the award Pleaase show your previous job same same like this before Thank you

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    VHDL Project Đã kết thúc left

    Hello everyone, I have to do a project in vhdl language. I have a list of 10/15 projects from which I have to choose one. The to-do list is: 1) report on the work done; 2) source code (in VHDL or other languages); 3) any examples for the code. The report typically consists of: - An overview of the topic. - A description of the methodology followed to carry out the project highlighting what are thought to be the most interesting contributions of the work done. - A high-level description of the code (it doesn't matter to put all the listings) and any instructions for use and compilation. - A description of the results obtained (simulations, statistics, algorithm outputs).

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    I have a MATLAB code and want this to be converted to HDL code using HDL Coder feature available in MATLAB. I have attached the error what i am getting currently

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    ASIC designer -- 3 Đã kết thúc left

    One of the most prestigious companies in the field of ASIC Design is looking for a talented Digital ASIC Designer, especially in the field of artificial intelligence algorithms. Required capabilities and skills are as follows: *Holding a bachelor or master's degree in electronics *Having adequate knowledge of digital design *Proficient in digital flow *Familiar with Verilog, VHDL languages *Experience with EDA tools from Cadence, Mentor, and Synopsys(SOC design & encounter) *Experienced in Transform specification from RTL to silicon CMOS circuitry *Ability to analyze designed circuits and optimizing them *Proficiency in problem solving *Ability to interact and collaborate with R&D colleagues *Experience with tapeout is preferred.

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    Using Pynq Z2 FPGA to connect a camera (OV7670 - CMOS Sensor), and then display the video on a monitor through HDMI output. The Project is built using VHDL language and IP blocks. The purpose of this it's to build also nurual network to recognize a face/person so the camera can follow the object using servo motor.

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    Hi, I'm looking for someone who buys some cans of "Red Bull Vị Cà Phê Ủ Lạnh" in Vietnam for me and ships it to Germany. This is what I'm looking for:

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    Địa phương
    $200 Giá đặt trung bình
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    vhdl expert Đã kết thúc left

    I want Signal processing and VHDL(Quartus Application) expert.

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    We have a HP DL360 server with vmware with Digium E1/T1 card. We wish to configure the same as our PBX for PRI line and configure all features step by step as needed. Guidance on correct setup is expected from the freelancer.

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    5G RAN FPGA Design Đã kết thúc left

    We have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools – Mi...

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    A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erro...controle de erros. Isto pode ser feito através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa quando um...

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    C++ DirectShow camera filter Đã kết thúc left

    We need to develop a C++ DirectShow filter that does the following: A. configuration: (using interop...the input pins of the given output camera (camera_out) B2.2 - we already have a virtual camera implementation and installer, it will be provided. C1.1 - if there is a new frame from the incoming camera (camera_in) there will be boolean that indicates it. this boolean will be set to false once the new frame has been requested by the external program. E. test program: E1 - a test program will be provided showing control over the process, selecting a camera, and a virtual camera and writing a text with the current fps on the output frame. F. installation script: F1 - an installation script for the filter will be provided as part of the ...

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    FPGA Design for Terasic board Đã kết thúc left

    1.VHDL code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.

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    Script rpc command Đã kết thúc left

    Create a script that creates wallets on custom nano node then generates random transactions and transactions data must be saved in a databases. interface server logs script must be able to create 1 wallet per second script must be able to generate...Formula: RANDOM BETWEEN TERMINALS(0;NB wallets) x RANDOMBETWEEN(Tlow;Thigh) backup: number of transactions on the loop, total number of transactions, average transaction per wallet, duration of the loop in seconds, total duration of the loops in seconds, total duration of the loops in hours, total duration of the loops in days DB1 DB2

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    SOC Verification Đã kết thúc left

    ...verification, preferably baseband/ controller side 2. Experience in Industry standard protocols ARM Interconnects(AHB, APB), SPI, UART, I2C, DMA, Serial Flash, Security and Encryption. 3. Full chip SoC (C and SV based), Subsystem and Block/IP level verification. Test Bench generation with ability to run embedded C programs. Must have experience of 2-3 SoC verification. 4. Experience in HDL(Verilog, VHDL) and HVL(System Verilog, Specman) based functional verification. Experience in code coverage. 5. Experience in Verification methodologies(UVM, OVM and eRM). language simulation (Verilog-AMS, SystemVerilog). 7. Experience in Mentor, Cadence and Synopsys simulators. 8. Build automated Test bench and regression environments from a scratch. Should be able to write a test plan and gen...

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    I want to receive VOICE DATA Calls... like GSM MODEM calls... being online nonstop.. like 9600 bps.. just having as conneecion .... I have so far 15.000 clients.. in slovakia... havig sold to them each... a collection of 25x CREDIT CARD terminal... which are online by default... using TCP/IP .... as well as I had wanted you to switch somehow them all to be 24h online using GSM/LTE /. UMTS model analog conneciton.... as SECURE direct call.... .s it´s best.... we really try to generate secure PHONE-network minutes... like we use cIRCUITS instead of DATA PACKETS.... we. just have of course not paid by minute... but to the O2 or. T-MOBILE or VODAFONE... we not pay by minute... we pay just a flat-rate.. like every day..... as this is the best... we just stay always online... during 7am - ...

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    INSTALL HYLAFAX ON A NAKED SERVER - LIKE A OWN ROOT SERVER ON DEBIAN... JUST FOR BEING READY TO BE T.38MODEM READY AND OPERATE WITH CISCO AS400 GATEWAYS IN BEING ABLE TO SEND OUT FAXES ON 160X E1 FAX LINES AND EVEN RECEIVE FAXES .... WE ARE NEEDING AS VM-TELECOM SRO IN SLOVAK REPUBLIC... WHICH IS OUR BUSINESS OPERATING AS VOIP TELCO COMPANY... WHERE I TRY TO ESTABLISH A OWN WEBPAGE... BEING ABLE TO SIGN UP FOR EVERYBODY IN THE WORLD ... FOR A OWN FREE FAX NUMBER.... AND SEND OUT FAXES... TO THE WHOLE WORLD... INCLUDING CURRENTLY "UKRAINA" AS COUNTRY +380 AS TELEPHONE NUMBER...THAT YOU CAN SEND TO UKRAINE COUNTRY FREE OF CHARGE AS MANY PAGES AS YOU WANT... -YOU EVEN SHOULD BE ABLE TO RECEIVE FAXES... SINCE IN EVERY CITY WE HAVE LOCAL TELEPHONE NUMBERS... WHERE WE HAVE THE...

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    Travelling the graphs - Java Đã kết thúc left

    ...whitespace is not allowed - All nodes are single, uppercase letters. - Edges are separated by a single space. - Distances are specified as unsigned integers - The sequence of edges is not ordered in any specific way. Output: - It is one line. - Contains no whitespace. - If errors are present, print te first of below listed errors (e.g. if E1 and E2 are present, print "E1") - If no errors are present, print the route using the representation as described below. Errors E1 - Input syntax error E2 - Logical input error E3 - Failed to find a suitable route Logical input errors are duplicate definitions of edges, specifying either a start or destination node (second line) that is not actually defined in the graph(first line), disconnected graphs, or more than...

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    We need a project done in Morse code encoder and decoder in VHDL. Our project contains 2 parts a transmitter and receiver. The transmitter part receives the text(ASCII) from the PC(user) via UART receiver and transmits the text to morse code encoder(converts text to morse code). The morse code pattern then is sent to an led. Dot(.) corresponds to LED on and dash(-) LED off. The receiver part has a photo diode which reads the blinking of the led(morse code) and data is transmits to Morse decoder where it is converted back to ASCII. The converted ASCII is then transmitted to end user PC for display. We have already designed the top level top level block diagram. we now need the source codes(entity and architecture) for the blocks and test benches for all blocks for simulation...

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    STM32CubeIDE and VHDL quartus Đã kết thúc left

    STM32 toolchain and also vhdl design with report describing the procedures

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    quartus and modulsim Đã kết thúc left

    i want some vhdl coding simulating with test bench on modulsim and a report

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    This project requires basic knowledge of digital electronics and VHDL coding.

    $14 / hr (Avg Bid)
    $14 / hr Giá đặt trung bình
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    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $20 - $67
    Niêm phong
    $20 - $67
    3 lượt đặt giá

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $40
    Niêm phong
    $7 - $40
    5 lượt đặt giá

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $41
    Niêm phong
    $7 - $41
    7 lượt đặt giá
    Digital Electronics and VHDL Đã kết thúc left

    Need someone expert in Digital Electronics and VHDL programming. More details will be shared in private chat.

    $7 - $34
    Niêm phong
    $7 - $34
    4 lượt đặt giá
    $92 Giá đặt trung bình
    1 lượt đặt giá

    Professional and proficient in the following areas Boolean Algebra and Logic Design  Number systems  Basic Theorems of Boolean Algebra  Canonical and Standard Forms  Logic Gate Implementations and Characteristics: ...Logic  Latches  Flip Flops  Finite-State Machine (FSM) Model  Synthesis and Analysis  Designing State Machines using State Diagrams  Designing State Machines using ASM (Algorithmic State Machine) Charts  State Minimisation, Optimisation and Timing. Hardware Description Languages (VHDL)  Combinatorial descriptions  Delta Delays  VHDL hierarchy (Entities, modules, instantiation)  Language constructs (conditional assignment, selected assignment)  Synchronous descriptions (processes, if, case)  VHDL test benches  Synthesis considerations

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    vhdl RISC processor coding Đã kết thúc left

    I need a vhdl master to code a RISC processor with multiple components. I will give the detailed information.

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C , C++

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    Help with VHDL Đã kết thúc left

    I have to implement a pipelined DLX processor. I have already constructed the single staged processor. However, I will need you to do the pipelining part which would include the pipelined control, and relevant harard detectors, forwarding unit, and bypassing mechanisms. The project now has been implemented using a supermodular approach where I have tried to make the VHDL codes for the smallest units and then built them upwards in the schematic. I will need the schematic of the pipelined dlx too. here is the drive link with all the files for your reference I have a certain benchmark to run which i will share once i get to design it but the i will need the isim simulations of the entire processor as a proof that

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    VHDL and risc-v LAB work . Đã kết thúc left

    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

    $30 - $250
    Niêm phong
    $30 - $250
    9 lượt đặt giá
    VHDL and risc-v LAB work Đã kết thúc left

    hi there i need an electrical or electronics engineer who is expert in VHDL AND RISC-V for simple task more details will be shared with the suitable candidates in the inbox regards

    $30 - $250
    Niêm phong
    $30 - $250
    5 lượt đặt giá

    hello, please contact me if you are proficient in the fields above

    $200 (Avg Bid)
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    The project involves creating an outbound dialer software with IVR functionality.: • Develop a system that is capable of making bulk calls to recipients. • The system must be able to be hosted online and be able to connect to operator E1/SIP Trunk. • The system must be able to schedule phone calls. The system must have a phone book, that includes name, number and sex (male or female) fields, the most important field is the number. The ability to create a group should also be available. • The system should be able to create different Campaigns (Campaign creation). • The system should be able to create IVR Menu’s for specific campaigns. Example Campaign: Training people about financial literacy in rural areas, the course has 6 lessons which will be de...

    $767 (Avg Bid)
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    Assalam o alaikum !!! We are looking for electrical engineers to join our team and work on different projects related to following domains of electrical engineering: 1) Control System 2) Satellite communicati...related to following domains of electrical engineering: 1) Control System 2) Satellite communication 3) Radio frequency and microwave circuit design 4) VLSI techniques 5) Radar theory and satellite communication 6) Intelligent and adaptive systems 7) Digital design 8) Asic design Freelancers must be proficient in following: 1) Matlab / Simulink 2) Proteus 3) Multisim 4) pspice 5) LTspice 6) VHDL/Verilog coding What I am expecting: 1. Dedication to the work 2. On time delivery of work without any delay 3. Well arranged and properly formatted reports with plagiarism count...

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    We are looking for electrical and electronics engineers with good experience in following areas: • Embedded C Programming. • VHDL/Verilog, LabVIEW/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. Feel free to place your bid and mention your areas of expertise in your proposal. we highly encourage new freelancers to apply for this post.

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