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    2,714 e1 vhdl công việc được tìm thấy, giá USD

    Tôi cần xúc tiến thương mại cho sàn CLoan - Sàn kết nối người đi vay và cho vay thế chấp bằng tài sản số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi khảo sát người đi vay :[đăng...

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    Hiện tại mình đang cần người tiếp tục phát truyện cổng truyện online của trang VipTruyen.Vn. Nếu bạn chuyên về php hãy tham gia dự án của bọn mình. Giá hoàn thành website là 3 triệu đến 5 triệu. Nếu các bạn muốn tham gia vào dự án của mình thì sẽ thảo luận thêm. Yêu cầu của m...

    $138 (Avg Bid)
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    Hiện tại bên mình đang chạy cho dự án sắp tới nên cần tuyển gấp 1 số freelancer về Apk iOS, Android, không phải game và design. Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghiệm, hợp tác lâu dài nhiều d...

    $991 (Avg Bid)
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    Looking for excel vba expert to help write a vba macro for following logic: Steps: Setting the period (first and last column where code should be executed) 1. First column = Today's date + E1 2. Last column = Today's date + F1 Push out logic 1. Match the AZs (E8:E24) to Gap/Excess (B63:B77) 2. For each matching AZs, if there is a excess (above 0, positive value) push the value in push/...

    $168 (Avg Bid)
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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $95 (Avg Bid)
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    Crear VM con Issabel en VMware 6 ngày left
    ĐÃ XÁC THỰC

    Somos un call center argentino que trabaja con multicampaña. Necesitamos crear 3 VM (Maquinas virtuales) en un servidor Dell. En las 3 VM se deben instalar la versión mas reciente de Issabel (Central Telefónica). Debe esta bajo SO Linux. Parámetros: Configurar troncales y rutas salientes: Troncales: 1 Gateway synway GSM de 16 canales 1 Gateway Openvox GSM 12 canales...

    $424 (Avg Bid)
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    Implementation of Fractional order Integer/ Derivative Using GL algorithm based VHDL on FPGA. simple code which i need.

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    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    Build Project - Altera DE2-115 FPGA board 1 ngày left
    ĐÃ XÁC THỰC

    I am currently using Altera DE2-115 FPGA board to configure it using Quartus 17 lite edition software and write the code in VHDL. We have to use QSYS, and NIOS II for Eclipse to write a program in C and to run the board. I am seeking some help in building this mini thing.

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    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

    $39 / hr (Avg Bid)
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    GL algorithm Expert 13 giờ left

    hello, I am looking for expert who build GL algorithm using VHDL. If you can do it, we will discuss in details.

    $36 (Avg Bid)
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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    5 lượt đặt giá
    FPGA/VHDL/Verilog Đã kết thúc left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

    $12 / hr (Avg Bid)
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    BCD adder VHDL using vivado Đã kết thúc left

    BCD adder vhdl code which detects an overflow using vivado

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    Please read carefully. You need to fix my code. I will sent to you in messages my project. Here is project description: The brightness measurement with help of PMODALS sensor ([đăng nhập để xem URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([đăng nhập để xem URL]) is to be used, which takes over the control. The resu...

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    GPS implementation Đã kết thúc left

    first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PCB of the board you have. U3 is ...

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    Project for Rajagopal S. Đã kết thúc left

    Hi Rajagopal S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. The brightness measurement with help of PMODALS sensor ([đăng nhập để xem URL] ) should be realized. For this purpose, the Basys 3 FPGA board should be used. Furthermore, an 8051 microcontroller IP core([đăng nhập để xem URL]) is to be used, which takes over the control. The resul...

    $221 (Avg Bid)
    $221 Giá đặt trung bình
    1 lượt đặt giá
    Clean, format and validate data Đã kết thúc left

    There are three data files 1. Organizers and Events Requirement Validate emails Remove records that do not have emails that validate Provide 2 files: a). File - with records that only contain validated emails b). File with old data - email not validated 2. Exporters Requirements a) Shorten Product Category Name - in all Product Category 1-7 columns Keep short name the same in all columns b) ...

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    Develop VHDL code for HX711 Đã kết thúc left

    Provide VHDL code and testbench simulation for ECP5 Lattice device (Diamond Studio) to read HX711 sample ([đăng nhập để xem URL]) And store it in 32bit register

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    Research help -- 3 Đã kết thúc left

    Hello, this is the task: "first task will be to use the xtal oscillator board that I designed and that works, together with the FPGA to read the GPS data and then synchronise the 40 MHz Voltage Controlled Xtal oscillator to the 1 second pulse produced by the GPS. That is called a frequency loacked loop. We will talk about the details of that on Monday. I have attached the schematic for the PC...

    $316 (Avg Bid)
    $316 Giá đặt trung bình
    8 lượt đặt giá

    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

    $33 / hr (Avg Bid)
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    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

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    Need example code de-10 Đã kết thúc left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Project for Marina L. Đã kết thúc left

    I need an "and" keyword search program, that I will describe as if it is in Excel, but it doesn't need to be an Excel program. In Excel column A, and in each cell down to a maximum of about 850,000 rows, there will be a list of words 50 to 1000 characters long. For example: A2: cat dog rabbit mouse trap... A3: table chair stool lamp ... A4: car truck motorcycle parts ... A5: comp...

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    More details will be shared via chat

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    More details will be shared via chat

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    Complex Signal Mixer VHDL Đã kết thúc left

    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

    $69 (Avg Bid)
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    5 lượt đặt giá

    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

    $103 (Avg Bid)
    $103 Giá đặt trung bình
    15 lượt đặt giá

    my project is about lipstick made from natural organic materials. High Quality My website in Vietnamese, you can make it with english than i give you the translation for vietnamese version I need the website easy to SEO with all tag / onpage SEO. + Chat and call button + Link to facebook pages, likes and share button + Faecbook pixels for facebook ads intergrated to action of users + Google ana...

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    Map page will be full map with 2 layer: Origin layer (from OSM) and KML layer KML layer will be provide as in attachment User interact with map will be similar to wikimapia in which user hover over a place it will light up (see attached image) when click to a place it will show custom content with link to forum custom content is similar like this http://wikimapia.org/#lang=vi&lat=20.944607&...

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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

    $222 (Avg Bid)
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    I have a map with coordinates (attached) I need a program that allows me to easily plot the location of accidents on this map. if i have a list of accidents, (say E1, A4, J7 etc) I need to be able to enter those coordinates and see them plotted on an online version of this map - (should be shows as a Red Dot or something that is small but visible) This needs to be highly interactive User Friend...

    $104 (Avg Bid)
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    Project for Jin Q. Đã kết thúc left

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

    $30 (Avg Bid)
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    Project for Nick B. Đã kết thúc left

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

    $30 (Avg Bid)
    $30 Giá đặt trung bình
    1 lượt đặt giá
    Project for Jin C. Đã kết thúc left

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

    $30 (Avg Bid)
    $30 Giá đặt trung bình
    1 lượt đặt giá
    Temperature sensor and FPGA Đã kết thúc left

    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

    $62 (Avg Bid)
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    Magento 2 issues fix Đã kết thúc left

    E1. Registered users are not able to use the eway payment shows as invalid card but with guest users it is working. E2. Few design changes on the front end page, 1) the Logo should be increased 2) when the product is added to the Cart through mobile, the search and cart are getting overlapped and 3) remove the address from the contact us E3. During the registration, the mobile number validati...

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

    $10 (Avg Bid)
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    FPGA and Vhdl expert needed Đã kết thúc left

    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

    $20 (Avg Bid)
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    I posted this a couple weeks ago but decided that the process was not in the direction I want to go for the future. I deleted the original post and welcome those that placed a bid to do it again. I am replacing my current E1 system that was developed to manage psychic calls, due to changes to the Telecommunications industry in Australia and am moving towards SIP service providers to meet my need...

    $351 (Avg Bid)
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    Wanted Online FPGA Tutor Đã kết thúc left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

    $105 (Avg Bid)
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    Existing Issues / Fixes Required: E1. During the registration, the mobile number validation should only be 04XXXXXXXX but not rest of the letters (048XXXXXXX consider as invalid phone number but it is actually valid phone number) E2. When customer selects the product and click on Cart, there is a Sign in option that displays on top side and it is observed that – the sign in from there is n...

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    FPGA Development Đã kết thúc left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

    $58 / hr (Avg Bid)
    $58 / hr Giá đặt trung bình
    19 lượt đặt giá
    Filtro de 3 bandas en vhdl Đã kết thúc left

    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Counter in VHDL Đã kết thúc left

    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

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    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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