Tôi cần xúc tiến thương mại cho sàn CLoan - Sàn kết nối người đi vay và cho vay thế chấp bằng tài sản số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi...số. Chiến dịch của tôi là tạo độ hút khách hàng có nhu cầu vay hoặc đi vay trong thị trường giao dịch tài sản số qua cách hoàn thành những câu hỏi khảo sát người đi vay : người kiếm tiền: Những người hoàn thành khảo sát và để lại thông tin cá nhân sẽ được nhận phần quà trị giá 10$ tại Clo...
Hiện tại mình đang cần người tiếp tục phát truyện cổng truyện online củ...hãy tham gia dự án của bọn mình. Giá hoàn thành website là 3 triệu đến 5 triệu. Nếu các bạn muốn tham gia vào dự án của mình thì sẽ thảo luận thêm. Yêu cầu của mình là các bạn tiến hành sửa chữa và nâng cấp cổng truyện theo yêu cầu của mình. Các bạn tải bản phác thảo của mình tại: %A3n+Th%E1%BA%A3o+Thi%E1%BA%BFt+K%E1%BA%BF+C%E1%BB%95ng+Truy%E1%BB%87n+Ho%C3%A0n+Ho%C3%A0n+Ch%E1%BB%89nhVipTruyen+%283% Mình đang ở Sài Gòn, nên muốn làm việc với những người...
Hiện tại bên mình đang chạy cho dự án sắp tới nên cần tuyển gấp 1 số freelancer về Apk iOS, Android, không phải game và design. Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghi...Bạn nào có kinh nghiệm về các lĩnh vực này thì bid giá nhé. Bên mình dự tính xây dựng team có kinh nghiệm, hợp tác lâu dài nhiều dự án. Các bạn có thể giới thiệu bạn bè tham gia nhóm outsource này. Budget chi phí cho phần outsource không cố định, phụ thuộc vào module nhận thầu....
Hello, I'm hiring a dev who's very hot with FGPA. Need him to create cryptocurrency miner/blockchain. Specificly Xilinx Alveo U200 & U250 Cards. I can pay a lot. Contact me I'm very active. #FPGA - #XILINX #ALVEO #ALVEOu200 #ALVEOu250 #XRT #MINING #CRYPTO #DEVELOPPER #FREELANCER #FREELANCE
I need to implement a complete FPGA system using Verilog in Vivado Design Suite. Professional FPGA experts are required. Please find the details of the project in the attachment.
We have a HP DL360 server with vmware with Digium E1/T1 card. We wish to configure the same as our PBX for PRI line and configure all features step by step as needed. Guidance on correct setup is expected from the freelancer.
...have an internal project for 5G RAN FPGA design for DFE products: Skills: Job Description- Senior MTS RTL design 5G Product( 2 positions) · Candidate must have at least Bachelors or Masters EE - FPGA design experience (RTL Coding, comms, DFE(DPD, DUC, DDC, FFT, FIR, CFR) · Candidate must have verifiable experience for a minimum 6 years as a Verilog/System Verilog/ VHDL/RTL programmer with extensive Verification test bench development experience · Preferred prior project experience in 5G ORAN - RU/DU. DSP knowledge Matlab modeling is preferred. · eCPRI experience preferred . Special consideration will be given to those who have experience as 100G Ethernet or 10G Ethernet , IEEE 1588 · Knowledge of Queuing theory · Tools &nd...
A presença de erros em dados digitais é um problema frequente em sistemas computacionais que lidam com transmissão e armazenamento de informação. Em alguns contextos, como o de computação aproximada, admite-se uma taxa ainda maior de erros para alcançar uma redução no consumo de energia. Nesses casos, torna-se imprescindível o controle de erros. Isto pode ser feito através do uso d...através do uso de códigos detectores (e corretores) de erros, que são capazes de detectar (e corrigir) a informação corrompida através de redundância inserida nos dados. Nesse projeto, o objetivo é gerar um codificador baseado em paridade e um detector de erros que avisa qu...
...Tasks: - Tasks are going to be disclosed on a per candidate basis upon signature of the NDA. Job requirements: - Implement on-site SEO expertise - Implement on-site WPO expertise - Responsive design/design and implementation of a mobile-friendly version - Timely functional testing of core website elements - Debugging for potential security issues. - Client-side animations (preferably using Framer Motion but not necessarily) Tech stack: - - TailwindCSS - Git/Github - tRPC* - Prisma ORM* * Not essential, but knowing this will help you situate better in our existing codebase. Useful, however distinct, website references: Concluding remarks:
I need to design a Hilbert transform and test it in Matlab before implementing it on FPGA. I have never created a Hilbert transform with Matlab without the hilbert() function, and the function does not return coefficients. I can't find the documentation on how to do it. I need someone to help with it. The Matlab code must also use the filter on sample data and return complex values after the transform. You should provide the Matlab code used to create the filter and get the coefficients. I will pay $70 USD for the task.
Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
The goal of the project is to design both hardware (PCB) and software for a low cost,small sized, digital video transmit...The interested designer can choose any processor or RF IC as per their wish but QFN/QFPN based IC will be preferable as they are easier to the image sensors/camera module should also be integrated into the AIO flight Controller can be based on Allwinner T113-S3 microprocessor or an FPGA but should contain Gyroscope, accelerometer, pressure/ project report will be sent to the intrested designers on request. An AI SoM board based on Rockchip/FPGA will also has to be developed under the design. The prototyping task will be undertaken by ourselves only the design of the video transmitter and the flight Controller needs to be done.
Hello, I need a Lattice FPGA specialist to review my simple LCMX02 Lattice PLD design. I can not make it work, and some help is needed to understand why the PLD does not respond to the JTAG file. This is a very specific project, specifically for Lattice FPGA. I designed with other types of FPGA, and got stuck when I switched to Lattice family of parts. Thank you!
We need to develop a C++ DirectShow filter that does the following: A. configuration: (using interop...the input pins of the given output camera (camera_out) B2.2 - we already have a virtual camera implementation and installer, it will be provided. C1.1 - if there is a new frame from the incoming camera (camera_in) there will be boolean that indicates it. this boolean will be set to false once the new frame has been requested by the external program. E. test program: E1 - a test program will be provided showing control over the process, selecting a camera, and a virtual camera and writing a text with the current fps on the output frame. F. installation script: F1 - an installation script for the filter will be provided as part of the ...
code for SPI master to send data to a GPU. project setup for the customer's terasic FPGA board. assignment. demonstration of contents via zoom meeting. I will try to complete the project before the specified end date.
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project. We can discuss any details over chat.
Creating 2-chain Arbiter PUF on specific FPGA with 64-stages MUX for each chain. The output response PUF will be sent to external device, i.e. Arduino (microcontroller). On the other words, the output response PUF will be processed further on Arduino/microcontroller device
Create a script that creates wallets on custom nano node then generates random transactions and transactions data must be saved in a databases. interface server logs script must be able to create 1 wallet per second script must be able to generate...Formula: RANDOM BETWEEN TERMINALS(0;NB wallets) x RANDOMBETWEEN(Tlow;Thigh) backup: number of transactions on the loop, total number of transactions, average transaction per wallet, duration of the loop in seconds, total duration of the loops in seconds, total duration of the loops in hours, total duration of the loops in days DB1 DB2
It is required to generate arbitrary signals in FPGA for Real Time Controls using Servo Proportional Valve with Control signals of ( +/- 10 VDC ). The various types of other signal generation in FPGA besides Arbitrary signal can be Square, Sine, Triangular. Generation of white noise signal for Real time control is also required.
Need help with code and set up for SPI protocol to send data from an FPGA to a GPU, explain code/software procedure and wiring. can forward technical specs for both devices to be used
I need to show up my services so, I decided to develop some pages (4-5) on wordpress. Planned to use framer template from themeforest. Looking for a developer who can develop wordpress website with clean and compact responsive design. here are some requirements before apply 1. Good in design understanding 2. Performance 3. On page SEO
Hi Islam Muhammad S., I noticed your profile and would like to offer you my project.
A complete color sorter Machine Firmware needs to be converted into Intel Quartus Project, The project contains IP Cores as well as softcore processor and the verilog coding part, All these to be integrated as a single bit file and to be implemented it on a Cyclone V FPGA Board.
Hi. Attached a few spike from scope capture. Need at least 8 channels simultaniously. 1. how to get detect these with a precision of 1mV? 2. how to get the value in stm32? (worked with these a lot) (or do we need an fpga) Freq is 200hz at first. Looking to get to 1 khz in the near future. Duration of the spike is only 5 to 12 microseconds. What is the best way to do this precisely ? heard tons of ideas (peak-detect circuit, 20 msps adc, etc ) , but need real proven experience. !!! please apply only if done this succefully. In the opening bid propose direclty your solution. Biggest bids will be disqualified. Stop bidding the top of freelancers brackets. No B*****S approach. Will be paid only if it WORKS! Need STM32 code, parts id, and pcb design.
The project requires an Embedded Programmer having experience in Driver Programming for FPGA cards, PCIe Interface and YOCTO as well as upbringing the Linux OS. Please DO NOT APPLY, if you DO NOT HAVE THE REQUIRED EXPERIENCE.
I need framing plans for a dormer additon to my 1.5 story bugalow house. After talking with a framer, we decided to go full width of the house, extend exterior walls to 8 feet and capture 4/12 pitch on a gable roof. The size is approximately 14 x24 feet.
I need a survey paper based on 3 articles at your choose from with publication date more recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, ...recent then 2010. The articles has to be based on one topic from the following. Theme variants: A. Digital signal processor architectures (e.g .: DSP, VLIW, etc.) B. Micro-architectures optimized for digital signal processing (e.g., multi-port memory, SIMD register banks, multi-core, multi-threading, etc.) C. Accelerators for digital signal processing (rapid deployments / energy efficient with FPGA, GPU, etc.) The paper must be written in latex format. 4 pages, 3-4 figures (explained) and also some references from other articles.
I want to receive VOICE DATA Calls... like GSM MODEM calls... being online nonstop.. like 9600 bps.. just having as conneecion .... I have so far 15.000 clients.. in slovakia... havig sold to them each... a collection of 25x CREDIT CARD terminal... which are online by default... using TCP/IP .... as well as I had wanted you to switch somehow them all to be 24h online using GSM/LTE /. UMTS model analog conneciton.... as SECURE direct call.... .s it´s best.... we really try to generate secure PHONE-network minutes... like we use cIRCUITS instead of DATA PACKETS.... we. just have of course not paid by minute... but to the O2 or. T-MOBILE or VODAFONE... we not pay by minute... we pay just a flat-rate.. like every day..... as this is the best... we just stay always online... during 7am - ...
INSTALL HYLAFAX ON A NAKED SERVER - LIKE A OWN ROOT SERVER ON DEBIAN... JUST FOR BEING READY TO BE T.38MODEM READY AND OPERATE WITH CISCO AS400 GATEWAYS IN BEING ABLE TO SEND OUT FAXES ON 160X E1 FAX LINES AND EVEN RECEIVE FAXES .... WE ARE NEEDING AS VM-TELECOM SRO IN SLOVAK REPUBLIC... WHICH IS OUR BUSINESS OPERATING AS VOIP TELCO COMPANY... WHERE I TRY TO ESTABLISH A OWN WEBPAGE... BEING ABLE TO SIGN UP FOR EVERYBODY IN THE WORLD ... FOR A OWN FREE FAX NUMBER.... AND SEND OUT FAXES... TO THE WHOLE WORLD... INCLUDING CURRENTLY "UKRAINA" AS COUNTRY +380 AS TELEPHONE NUMBER...THAT YOU CAN SEND TO UKRAINE COUNTRY FREE OF CHARGE AS MANY PAGES AS YOU WANT... -YOU EVEN SHOULD BE ABLE TO RECEIVE FAXES... SINCE IN EVERY CITY WE HAVE LOCAL TELEPHONE NUMBERS... WHERE WE HAVE THE...