Fpgacông việc

Implement a high-accuracy, real-time vehicle license plate recognition system on the Kria KV260 FPGA using Verilog and an AI-based model (e.g., YOLO)

cần code verilog theo bài báo này

Viết Inverse kinematics chạy trên FPGA của Xilinx

Hi Duc D., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Khanh L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Kevin N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Tiep N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Lic T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Quang T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Huy, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Hi Hong L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Van Phu, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

Quan, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

Long, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

Long, ti6i cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo tôi là bay sau khong chin bay nam chin ba bay tam. Locson

FM transmitter(Xilinx)-fpgaFM transmitter(Xilinx)-fpgaFM transmitter(Xilinx)-fpga

We are seeking an experienced Zynq UltraScale+ FPGA engineer to assist with the bring-up of our ZCU104 board, focusing on camera interface and testbench development. The ideal candidate will have hands-on experience with FPGA design, verification, and debugging. You will be responsible for ensuring the functionality of the camera interface and developing a comprehensive testbench. Knowledge of embedded systems and familiarity with relevant development tools is crucial for this role.

I’m updating the firmware for an STM32-based design and need an experienced C++ developer who is comfortable inside STM32CubeIDE. The codebase already compiles and runs on the microcontroller, but several features still require clean, well-structured implementation, performance tuning and thorough testing directly on the hardware. You’ll be working exclusively with STM32 microcontrollers; no FPGA or other targets are involved. Please be ready to pull the current CubeIDE project from my repository, build it as-is, and then extend it in C++17 (or later) while respecting the existing HAL layer and project structure. Deliverables • Updated CubeIDE project with the new or fixed functionality fully integrated • Clear build instructions and a short change log so...

...existing electrical interfaces to the MYIR board unchanged and minimizing or avoiding FPGA/firmware changes as much as possible. Scope of Work (High Level) - Integrate two RF transmit chains on one board - Use a shared reference oscillator and PLL for both RF paths - Replace discrete RF filters with compact off-the-shelf RF filters - Replace legacy power regulators with modern, small LDOs - Add RF routing options: - Combiner for both RF outputs - Splitter to provide up to three RF outputs - Focus on size reduction and clean, manufacturable design Key Constraints - MYIR Zynq-7020 board and its connectors remain unchanged - Signal interfaces to the Zynq better stay compatible with the existing design - FPGA and software changes should be minimal or not required - PCB manuf...

...Tech academic projects in the Embedded / ECE domain for Indian universities. We are looking for one reliable freelance Embedded Systems developer for long-term, project-wise collaboration. This is not a full-time job. Work will be assigned per project. Scope of Work Develop Embedded / ECE hardware or simulation-based projects Support domains like: Embedded Systems, IoT, ARM / Microcontrollers FPGA / VLSI (optional) Control systems / Sensors / Automation (as applicable) Deliverables per project: Working code / simulation / hardware logic Result screenshots / output proof Project report content (chapter-wise) Project PPT content IEEE conference paper draft Scopus journal extended paper draft Support 1–2 rounds of revisions based on guide/reviewer comments Requ...

Assalam o alaikum, I am looking for electrical engineers having expertise in following areas:  Embedded C Programming.  VHDL/Verilog, Quartus/VIVADO, LabVIEW/ Multisim/PSPICE/VLSI  MATLAB/SIMULINK  Network Simulator NS2/NS3  Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC, STM32 and ESP32.  IDEs like Keil MDK V5, ATmel studio and MPLab XC8.  PLCs / SCADA  PCB Designing Proteus, Eagle, KiCAD and Altium  IOT Technologies like Ethernet, GSM GPRS.  HTTP Restful APIs connection for IOT Communications. Actually I have multiple projects in different domains of electrical engineering and I already have a team of engineers working on them but due to workload I am looking for few more engineers to be a part of my team and work with us on regular basis.

...Microcontroller and embedded targets rotate between Arduino-based boards, Raspberry Pi modules, and mid-range FPGAs, so comfort switching among those platforms is essential. Core expectations • Design or refine circuits and document the rationale behind every component choice • Build and verify MATLAB/Simulink models that correlate with hardware behaviour • Prototype on Arduino, Raspberry Pi or FPGA as the problem dictates and capture results in a concise technical report • Deliver well-formatted reports (Word or LaTeX) that include schematics, simulation plots, and test data I review drafts collaboratively, offer rapid feedback, and release milestones as each design, simulation, and report section is accepted. If you graduated recently, have the abo...

I need a seasoned PCB designer located in Pakistan who can take a concept right through to production-ready files. The boards you create must interface reliably with Arduino, Raspberry Pi, and FPGA modules, so familiarity with their pinouts, signalling levels, and power budgets is essential. You’ll start by translating my functional requirements into clear schematics, then handle the full PCB layout, component selection, and DFM checks. I expect well-organised source files plus manufacturing outputs—Gerbers, drill files, pick-and-place, and an accurate BOM—with every revision traceable. If you prefer Altium, KiCad, Eagle, or OrCAD that’s fine; just let me know which environment you’ll use so I can open the files on my end. Because these boards may...

I'm seeking an experienced FPGA developer to help debug logical errors in existing VHDL code for a Lattice Semiconductor MachX03 development board. Key Requirements: - Expertise in VHDL - Experience with Lattice Semiconductor FPGAs - Strong debugging skills, especially with logical errors Ideal Skills and Experience: - Proven track record in FPGA development and debugging - Familiarity with MachX03 specific features and tools - Ability to provide clear, concise solutions and documentation Looking forward to your expertise!

...management. FPGA Image Processing 1. I need to work on a project and implement a novel idea related to FPGA-based image processing. 2. I have the following tools available: o Xilinx Vivado 2018.2 and Xilinx Vivado 2025.1 o MATLAB 2024a and Simulink o Python simulation tools. Task: • Read an image (in BMP, .hex, or .coe format). or camera • Refer to a recent IEEE research journal (preferably from the year 2025) for guidance or inspiration. (Focus on novelty, performance (area,speed, resource usage,etc..), and application relevance.) "use any algorithm and architecture" • After completing the work, I aim to publish the results in a Science Citation Index Expanded (SCIE)/ SCI journal. • Give me dummy Word document, respective results in zip fil...

...presentation-ready diagram that shows our network architecture in a way that looks great on a slide deck. The look should stay firmly in the minimalistic camp—simple lines, flat colours, no shading—yet still feel polished and professional. Please represent these entities with matching iconography: • Cell tower • RF probes • FPGA module • Neural-network processing block The flow is straightforward: signal originates at the cell tower, passes through the RF probes, feeds into the FPGA for conversion, and ends up in the neural-network section. Arrange the elements so that this path is obvious even to a non-technical audience. Deliverables • Editable source file (AI, Figma, or SVG) • High-resolution PDF or PNG, 16:9 ...

I need an expert in low-latency data acquisition systems. We are utilizing FPGA-based DMA hardware to interface with a running application. I require assistance in mapping internal data schemas and establishing reliable logic paths for an external Python controller. The ideal candidate has experience with LeechCore or similar hardware-interfacing libraries and understands C++ memory management.

I am assembling a 30-member core team to take India f...Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter. Key acceptance criteria • Architecture spec frozen within 60 days of team formation • First FPGA bring-up by month 6 • Tape-out-ready GDSII no later than month 12 If you’re passionate about putting India on the global semiconductor map and ready to own a slice of ...

I am assembling a 30-member core team to take India f...Solid command of SystemVerilog/VHDL, C/C++, Linux kernel or Yocto, scripting, and modern EDA toolchains (Synopsys, Cadence, Siemens) is expected. What to include in your application Show me clear evidence of relevant experience—projects you’ve taken from spec to silicon or to FPGA prototypes, particularly for computing devices. Mention any industry connections (fabs, EDA vendors, IP houses) you can bring; they matter. Key acceptance criteria • Architecture spec frozen within 60 days of team formation • First FPGA bring-up by month 6 • Tape-out-ready GDSII no later than month 12 If you’re passionate about putting India on the global semiconductor map and ready to own a slice of ...

Your task is to code an RGB to MIPI DSI pipeline in a Lattice LIF-MD6000 FPGA. The objective is to simply succesfully initialize and show a video output on a specific VR-type MIPI DSI display of which the full datasheet will be provided. The display requires a specific initialization procedure that includes DCS and Manufacturer commands. The display can be used in both 4x2 data lanes or 4x1 data lanes by using Vesa DSC compression. The latter shall be used and a compression layer shall be included in the pipeline. The pipeline shall use as little LUTs and resources as possible, and to do so it shall use the hard d-phy interfaces included in the FPGA. A basic test pattern generator may be used to show functionality for the video output.

...brief is image-processing: sharper live visuals, instantaneous frame-by-frame analysis, and on-screen flags whenever the algorithm spots a potential anomaly. All processing must happen in real time without introducing perceptible latency to the surgeon’s view. My current hardware outputs standard HDMI and records to DICOM, so your code should sit either between the camera head and the display (FPGA, GPU box, or high-performance PC is fine) or run as a software module on the workstation already attached to the scope. OpenCV, CUDA, TensorFlow, or similarly robust libraries are welcome—just keep licensing constraints clear. Deliverables • Executable or deployable source that enhances image clarity, performs real-time analysis, and triggers automated anomaly detect...

I am seeking a multi-disciplinary expert or a small team to assist in a high-fidelity hardware research project focused on PCIe device emulation and DMA-based memory forensics. The goal is to develop a custom FPGA-based solution that can perfectly mimic a legitimate consumer PCIe device (e.g., Network or Storage Controller) to pass low-level system integrity checks. Key Responsibilities: Emulation (FPGA/Verilog): Develop custom firmware for an Artix-7/35T/75T FPGA board to emulate a real-world donor device's configuration space and TLP behavior. Development (C/C++): Create a high-performance Windows/Linux driver for direct memory access via the PCIe bus, ensuring stability and low latency. Analysis: Design a system to read and analyze specific application me...

FPGA + SDR (ADRV9009) System Development – ZC706 Platform Project Description We are looking for an experienced FPGA / SDR engineer to develop a complete ADRV9009 + Xilinx ZC706 based SDR system. The project includes RX/TX signal processing, FPGA firmware development, Linux integration, and Ethernet-based control and data streaming. Hardware Platform • FPGA Board: Xilinx ZC706 Evaluation Board • RF Front-End: Analog Devices ADRV9009 SDR Development Board • System Type: Single integrated ADRV9009 + FPGA SDR system Interfaces • JESD204 (ADRV9009 - FPGA) • Ethernet (ARM/FPGA - PC) RX (Receiver) Requirements • Capture RF signals with 200 MHz instantaneous bandwidth • Configurable parameter...

We are looking for a proactive and versatile assistant to support operations, travel coordination, project management, and documentation activities within an FPGA and embedded systems company. This position is primarily remote, but occasional in-person visits to our main offices or participation in business trips within Europe (mainly Italy and Germany) will be required. You’ll collaborate directly with the company founder and CEO, helping streamline daily operations, audits, and international coordination. Key Responsibilities Travel & logistics: organize flights, hotels, and transfers for business trips; manage travel expenses and reimbursements. Project coordination: track tasks, milestones, and deadlines; assist in preparing reports and follow-up summaries. Documen...

I have an OLED panel wired directly to a Xilinx-based FPGA design and the existing display driver is outdated.

I am building a compact measurement and control module that marries an ESP32 with a small FPGA. The FPGA will handle real-time signal processing, while the ESP32 aggregates the results, pushes them to the cloud over MQTT, and serves a simple web dashboard. Core scope – Mixed-sensor support: the front-end must accept both analog and digital sensors. – Analog path: implement on-FPGA filtering before results reach the ESP32. – Digital path: straight-through capture with room for future logic extensions. – Two-layer PCB integrating the ESP32, FPGA and sensor interface components. – SPI-based hand-shake between the two chips. Key tasks • Design the sensor input circuitry and full schematic. • Write and verify VHDL/V...

I’m building an integrated computer system and need a specialist to take full ownership of the hardware side of its networking component. The objective is straightforward: create a router/switch that delivers markedly higher throughput than off-the-shelf options. You will translate my performance targets into a workable design, choosing the right switching ASICs or FPGA packet engines, laying out a high-speed, signal-integrity-friendly PCB, and planning for power, thermals, and EMI from day one. Experience with multi-gigabit Ethernet PHYs, SERDES routing, and design tools such as Altium or KiCad will be invaluable—we’ll lean on those skills to keep iterations to a minimum and get to the lab quickly. Deliverables I expect: • Complete schematics ready for revi...

...India that still needs its very first breath of life, and I want Zephyr running on it. The immediate goal is classic board bring-up: get the SoC to boot into Zephyr cleanly, prove that the console works, show me the GPIOs toggling, and hand back a minimal yet reproducible reference design so future work can build on top of it. Here’s what I expect from you: - Riscduino riscv based soft SoC on FPGA, need bring-up zephyr on this platform • Create or adapt the Zephyr board definition (device-tree, Kconfig, defconfig, pinmux, etc.). • Deliver a patch series I can upstream or re-apply, together with concise build and flash instructions that work on a fresh clone of Zephyr and the RISC-V toolchain. Acceptance is simple: I flash the image exactly as documented, Z...

...configure the Xilinx FFT IP for 8192 points, wire it to the chirp stream, and handle any required data-format conversions or hand-shaking. • Provide timing-compatible top level, constraints, and a self-checking test-bench that sweeps the chirp, captures the FFT output, flags the peak bins and dominant frequencies. Acceptance is straightforward: when I run the supplied simulation and then program the FPGA, I should see the chirp transition cleanly across the stated band and the FFT output highlight the correct moving peak without spurs or dropped samples. More projects to follow for right skilled engineer....

Code simulator and description for Basys 3 fpga board

...profiles should show hands-on success with real-time video streaming, image recognition, and advanced video compression while working close to the metal on custom hardware. Because these products live on constrained platforms, I’m especially interested in candidates who can pair the video know-how with strong embedded systems expertise, practical machine-learning integration, and, where relevant, FPGA development for acceleration. What I need from you is a curated bundle of CVs—each one clearly demonstrating the above skill mix, employment history that proves mid-level depth (roughly 3-7 years), and concise notes on why the candidate fits. Feel free to include any additional screening insights you believe add value. I’ll review the first batch, provide feedba...

I’m building a video pipeline on an Artix-7 XC7A200T board that carries two ADV7611 HDMI inputs and one SiI9134 HDMI transmitter. I need a complete Vivado project that captures 1080p video from both ADV7611 receivers, performs basic in-FPGA signal processing (frame buffering, colorspace conversion or simple image filter—whichever is cleanest to showcase the path), and then drives the SiI9134 so the processed stream displays correctly on an external monitor. The project must be written in synthesizable Verilog or VHDL, use the latest Vivado tool-flow, and include: • Top-level RTL connecting the ADV7611 I²C, video, and clock lines to the SiI9134 interface on the XC7A200T • A timing-clean 148.5 MHz pixel clock domain plus any required gearboxes or FIFOs f...

Also, have to record a short demo, and write a simple report.

...(EMI, safety). Your past projects should show that you have already solved comparable challenges and can back it up with real-world test data. Key deliverables (in discrete form): • Schematic and BOM with industrial-grade components • Magnetics design files and calculations • PCB layout (Altium, KiCad, or similar) optimized for thermal paths and low noise • Digital control firmware or DSP/FPGA logic, fully annotated • Simulation files (SPICE, PLECS, or equivalent) validating efficiency and THD • Prototype test report confirming output quality, protection triggers, and thermal behavior After awarding the project I’ll share the final power rating, enclosure constraints, and any branding-specific compliance marks so we can lock dow...

I am looking for an experienced FPGA developer to write functional Verilog code for interfacing a 1-wire secure EEPROM with a Zynq Zed Board. The EEPROM includes SHA-1 authentication. The deliverables should include: - Fully functional Verilog code for the interface. - Proper handling of SHA-1 authentication. - Compatibility with the Zynq Zed Board.

Design and implement a basic 8 Bit CPU on an FPGA board The implementation will use Verilog (or VHDL if preferred) and target a standard, widely available FPGA board like the Xilinx Coartex-A7 ensuring compatibility with Vivado. Deliverables • HDL source: well-commented modules for datapath, ALU, control unit, registers, and memory interface • Testbenches: simulation covering each instruction, plus a self-checking program counter/ALU regression • Vivado artefacts: implemented design, timing summary, resource utilisation report • Schematics: readable datapath and control diagrams (PDF or PNG) • Documentation: 4–6-page write-up describing micro-architecture choices and verification plan • Bitstream + demo program: ready-to-flash ...

I’m starting my final-year project by taking the MathWorks example “Designing a Guidance System in MATLAB and Simulink” and turning it into a hardware-in-the-loop demonstration that off-loads the control algorithms onto an FPGA—ideally the Altera DE2-115 I already have on my desk. Right now I’m at the initial setup stage, so everything is still in pure Simulink. Your role is to guide me through the FPGA-in-the-Loop (FIL) workflow, get the controller blocks synthesised, and prove they behave identically once they’re running on silicon. Sensor integration and data logging can wait; the immediate focus is control-algorithm work and, in particular, thorough algorithm testing after it lands on the chip. Deliverables • Partitioned Simuli...

Description: I am looking for an experienced embedded engineer / firmware developer with strong knowledge in Chip Whisperer Husky, FPGA/embedded C, and side-channel analysis (SCA). Phase 1 – Modify Husky Firmware Your tasks will include: Modifying the Husky firmware and capture pipeline to enable high-speed trace capture from smartcard reader pins (C1, C3, C7). Ensuring synchronized capture suitable for CPA, SPA, and EMV security analysis. Optimizing capture settings, buffering, and USB streaming for multi-trace datasets (250–500 traces per session). Phase 2 – Build a Miniature Standalone Husky-Derived Device After firmware modification is completed, the next milestone: Use the open-source Husky hardware + firmware codebase to design a miniaturized standal...

Assalam o alaikum,...design, simulation and report writing with zero plagiarism. (use of chatGPT highly prohibited). I am looking for experts who can deal FYP related to following domains of electrical engineering: Power Systems / Renewable energy systems Control Systems Signal Processing Instrumentation Engineering Internet of things Freelancers must be proficient with following: • Arduino/Raspberry Pi • FPGA | Verilog/VHDL • Proteus | TinkerCAD • Multisim | LabVIEW • MATLAB/SIMULINK & Python ***MOST IMPORTANT*** Applicants should be proficient in technical report writing and must have good command over proper formatting of final year reports by following their templates provided by different universities. Reports should be pl...

I need an FPGA expert to implement signal processing code for wireless communication. The baseline modulation technique is QAM, with multiple waveforms to be provided by us. Key Requirements: - Implement signal processing functions on FPGA - Support multiple modulation techniques, starting with QAM - Experience with wireless communication protocols - Proficiency in FPGA programming and hardware description languages (HDL) Ideal Skills: - Strong background in digital signal processing (DSP) - Experience with FPGA development tools and environments - Knowledge of wireless communication standards and practices - Ability to work with provided modulation waveforms Please include relevant experience in your bid. Expected completion: March 31, 2026