Bộ lọc

Tìm kiếm gần đây của tôi
Lọc theo:
Ngân sách
đến
đến
đến
Loại
Nhiều kỹ năng
Ngôn ngữ
    Tình trạng công việc
    3,107 fpga công việc được tìm thấy, giá theo USD

    cần code verilog theo bài báo này

    $62 (Avg Bid)
    $62 Giá đặt trung bình
    4 lượt đặt giá
    Viết bài tập Verilog Đã kết thúc left

    Viết Inverse kinematics chạy trên FPGA của Xilinx

    $2 - $8 / hr
    $2 - $8 / hr
    0 lượt đặt giá
    Project for Duc D. Đã kết thúc left

    Hi Duc D., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $30 / hr (Avg Bid)
    $30 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Khanh L. Đã kết thúc left

    Hi Khanh L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Kevin N. Đã kết thúc left

    Hi Kevin N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $19 / hr (Avg Bid)
    $19 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Tiep N. Đã kết thúc left

    Hi Tiep N., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Lic T. Đã kết thúc left

    Hi Lic T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    PHP
    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Quang T. Đã kết thúc left

    Hi Quang T., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $18 / hr (Avg Bid)
    $18 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Huy L. -- 2 Đã kết thúc left

    Huy, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Hong L. Đã kết thúc left

    Hi Hong L., tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $15 / hr (Avg Bid)
    $15 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Van Phu H. Đã kết thúc left

    Van Phu, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

    $10 / hr (Avg Bid)
    $10 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Quan D. Đã kết thúc left

    Quan, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là mot bay sau khong chin bay nam chin ba bay tam. Locson

    $10 / hr (Avg Bid)
    $10 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for hoangvsm Đã kết thúc left

    Long, tôi cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo, vi bơ của tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $5 / hr (Avg Bid)
    $5 / hr Giá đặt trung bình
    1 lượt đặt giá
    Project for Long D. Đã kết thúc left

    Long, ti6i cần giúp làm FPGA Altera. Nếu giúp được, xin LL với tôi. Za lo tôi là bay sau khong chin bay nam chin ba bay tam. Locson

    $5 / hr (Avg Bid)
    $5 / hr Giá đặt trung bình
    1 lượt đặt giá
    FM transmitter(Xilinx)-fpga Đã kết thúc left

    FM transmitter(Xilinx)-fpgaFM transmitter(Xilinx)-fpgaFM transmitter(Xilinx)-fpga

    $230 (Avg Bid)
    $230 Giá đặt trung bình
    2 lượt đặt giá
    Mining Pool -- 2 6 ngày left
    ĐÃ XÁC THỰC

    ...days, local server time, current BTC network difficulty, The Block number that the pool is currently working on, Report on how far past 10 minutes the last block found on the network, Server "Luck", blocks found by the pool in the past, Records of the payouts on each block found. 18. Identify the type of chip that is connecting to the pool so that stats can be made on which types of miners (CPU,GPU,FPGA or ASIC) are working on the pool with the option to show which type of chip has solved x number of blocks. 19. Pool stats should be dynamic so that they show miners their potential payout page to give active miners an idea of what their payout would be if a block was to be found at that time. 20. Pool source code built will be exclusively used for this project and not sh...

    $2402 (Avg Bid)
    $2402 Giá đặt trung bình
    66 lượt đặt giá

    Devlop a model to detect skin cancer using conditional GAN translation and apply on cnn models. Execute the model on fpga processor

    $312 (Avg Bid)
    $312 Giá đặt trung bình
    11 lượt đặt giá

    I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

    $68 (Avg Bid)
    $68 Giá đặt trung bình
    7 lượt đặt giá

    QPSK modulation and demodulation with Turbo Encoder/Decoder, Interlever, Channel Estimator, Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design d...Channel Equalizer, Pulse shaping filter, coarse and fine synchronization etc. Defined Parameters: Data Rate: 16kbps, 100kbps, 2msps Modulation Scheme: QPSK Bandwidth: 25KHz, 300KHz, 2MHz Sampling Rate: Twice of Data Rate Software: Vivado 2019.1 (for hardware design development) on Zynq 7035 and 7030. Linux Based OS to make Linux OS executable files. Hardware: Zynq 7030 and 7035 FPGA and AD9361 Tr...

    $6333 (Avg Bid)
    $6333 Giá đặt trung bình
    9 lượt đặt giá

    To interface lattice FPGA with ultrasonic sensor (5 )and lidar sensor(4) with the provision for connecting an MIPI based camera module (no AI stuffs),the FPGA would be connected to stm32h7 via SPI interface . More details via chat including the sensor type

    $149 (Avg Bid)
    $149 Giá đặt trung bình
    5 lượt đặt giá
    Mining Pool Đã kết thúc left

    ...local server time, current BTC network difficulty, The Block number that the pool is currently working on, Report on how far past 10 minutes the last block found on the network, Server "Luck", blocks found by the pool in the past, Records of the payouts on each block found. 18. Identify the type of "chip" that is connecting to the pool so that stats can be made on which types of miners (CPU,GPU,FPGA or ASIC) are working on the pool with the option to show which type of chip has solved x number of blocks. 19. Pool stats should be dynamic so that they show miners their potential payout page to give active miners an idea of what their payout would be if a block was to be found at that time. 20. Pool source code built will be exclusively used for this project and ...

    $481 (Avg Bid)
    $481 Giá đặt trung bình
    10 lượt đặt giá
    looking for FPGA developer Đã kết thúc left

    Looking for FPGA developer to write simple program on Intel Stratix board

    $116 (Avg Bid)
    $116 Giá đặt trung bình
    14 lượt đặt giá
    Intel MAX 10 FPGA PROJECT Đã kết thúc left

    completing design demonstration of work and explanation Report and final work -this includes all the recording of work -how and why

    $110 (Avg Bid)
    $110 Giá đặt trung bình
    1 lượt đặt giá

    Devlop a model to detec skin cancer

    $322 (Avg Bid)
    $322 Giá đặt trung bình
    11 lượt đặt giá

    Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

    $149 (Avg Bid)
    $149 Giá đặt trung bình
    45 lượt đặt giá
    PCB Design / Layout Đã kết thúc left

    Looking for an experienced designer / electrical engineer to move further with our products. We currently have 4 projects that involve ESP32, FPGA and MPUs. We're hoping to find someone who will be able to work on our other projects after completion of the first one. This particular project involves a 4 single layer board design using ESP32, solar power management, super capacitors and SPI display. We're looking for someone who is able to complete the project based on the requirements and is able to provide consultation on the future designs.

    $157 (Avg Bid)
    $157 Giá đặt trung bình
    55 lượt đặt giá

    Hello,I am looking for guys who could integrate the AD9361 with lattice FPGA series and also port some of the codes which were made fro the xilinx FPGA into the same lattice FPGA.

    $175 (Avg Bid)
    $175 Giá đặt trung bình
    6 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $55 (Avg Bid)
    $55 Giá đặt trung bình
    1 lượt đặt giá

    We have a need for a programmer for both microcontrollers and FPGAs to control I/O from a host computer to custom high channel count, high voltage drive electronics used to control deformable mirrors.

    $56 / hr (Avg Bid)
    $56 / hr Giá đặt trung bình
    13 lượt đặt giá

    accept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. optional de-interlacer (swit...source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board and any FPGA device can be used for testing it on. It is essential that the potential developer will provide the samples (with code fragments) of previous experience. More than 3 years of Verliog/ HDL experience ...

    $2000 (Avg Bid)
    NDA
    $2000 Giá đặt trung bình
    1 lượt đặt giá

    we have to give input images for that it should create a eigen face by using eigen values and eigen vectors and compare it with the given image matching or not in verilog so that I wanted to implement in the FPGA board I want it in gate level model

    $141 (Avg Bid)
    $141 Giá đặt trung bình
    5 lượt đặt giá
    SE-1 GUI rev 1 Đã kết thúc left

    We need to develop a GUI in a preact framework, using Javascript, interfacing to an FPGA via a FTDI chip over USB. I uploaded the mock up code we have running, showing some details in what we have thought. Base code is to be in GO.

    $38 / hr (Avg Bid)
    Gấp NDA
    $38 / hr Giá đặt trung bình
    9 lượt đặt giá

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    $143 (Avg Bid)
    $143 Giá đặt trung bình
    19 lượt đặt giá

    The objective is to create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new m...the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part from it. #verilog #matlab #imageprocessing #darkchannelprior #fpga...

    $108 (Avg Bid)
    $108 Giá đặt trung bình
    6 lượt đặt giá
    line following bot Đã kết thúc left

    I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.

    $14 (Avg Bid)
    $14 Giá đặt trung bình
    4 lượt đặt giá
    FPGA Engineer Đã kết thúc left

    We are in the need of FPGA Engineer for a SDR product. We want to maximize the Power Output of SDR (Software Defined Radio) with the use of Amplifiers. You can have remote access to customize the FPGA of the SDR + Amplifiers. Currently we have them already operational - however, we know that we need to tweak more to maximize this. No need to fully re-write the FPGA coding - it is truly tweaking the code based upon Technical Git / Manual information. Budget 500 - 750.

    $540 (Avg Bid)
    $540 Giá đặt trung bình
    17 lượt đặt giá

    Input(Live video) is accessed from the camera connected to the board and output should be displayed in the monitor connected to the FPGA board. and output should have a bounding box with a label of the detected object.

    $180 (Avg Bid)
    $180 Giá đặt trung bình
    6 lượt đặt giá

    For 10 years, poor FPGA BTC mining implementations, completely missed the big picture with excessively large, slow, power hungry designs. Researchers presented dozens of papers on how to make this better, completely missing the mark. This is your chance to get it right. Read this paper , then and look at their Verilog here to get a good understanding about state of the art FPGA BTC mining with verilog. Then apply that to YOUR FORK of the old standard in with an updated proxy for getwork. Clues follow to make FPGA BTC mining faster, smaller, and lower power, so that you will have REAL bragging

    $625 (Avg Bid)
    Nổi bật Bảo đảm Niêm phong Cuộc thi hàng đầu
    $625
    11 bài tham dự

    In this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to convert and modify the cod...

    $479 (Avg Bid)
    $479 Giá đặt trung bình
    18 lượt đặt giá
    FPGA system Đã kết thúc left

    Hi I need a expert in red pitaya.I want to design project using red pitaya

    $17 / hr (Avg Bid)
    $17 / hr Giá đặt trung bình
    15 lượt đặt giá
    Vhdl for video processing FPGA Đã kết thúc left

    We need a VHDL designer with expertise on video processing codec.

    $33 / hr (Avg Bid)
    $33 / hr Giá đặt trung bình
    18 lượt đặt giá

    We need a script to automate our FPGA design flow. Preferred in tcl language 1. Set the environment 2. Grab sources from repo 3. Run simulation and regression test 4. Run synthesis and place and route (vendor independent) 5. Generate reports 6. More than one project, we want to run it during night time

    $650 (Avg Bid)
    $650 Giá đặt trung bình
    18 lượt đặt giá
    FPGA design support Đã kết thúc left

    the company needs FPGA design services support for a multichannel DMA systes

    $40 / hr (Avg Bid)
    $40 / hr Giá đặt trung bình
    2 lượt đặt giá
    fpga video processing pipeline. Đã kết thúc left

    accept digital RGB input (24bit + HS VS DE) in one resolution, output digital RGB output (24bit + HS VS DE) in another resolution. Features required : 1. optional de-interlacer (swit...source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board and any FPGA device can be used for testing it on. It is essential that the potential developer will provide the samples (with code fragments) of previous experience. More than 3 years of Verliog/ HDL experience ...

    $4576 (Avg Bid)
    Nổi bật NDA
    $4576 Giá đặt trung bình
    13 lượt đặt giá

    I need to use Xilinx IIC IP on Artix board as a master, I used it in master mode and it didn't work well (The generated signal seems to be random) I tried the IP on Zynq platform and it worked well, but on Artix it beahves inproperly! I need someone to get it up and running on my chip.

    $171 (Avg Bid)
    $171 Giá đặt trung bình
    16 lượt đặt giá
    FPGA Expert Đã kết thúc left

    Xilinx ZCU104 MPSOC FPGA Expert

    $52 / hr (Avg Bid)
    $52 / hr Giá đặt trung bình
    4 lượt đặt giá
    I need a Verilog/Vivado expert Đã kết thúc left

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    $39 (Avg Bid)
    $39 Giá đặt trung bình
    10 lượt đặt giá

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    $37 (Avg Bid)
    $37 Giá đặt trung bình
    3 lượt đặt giá

    Objectives of this project are Benchmarking speed, ROM, and RAM usage of software implementations of Simon and Speck's ciphers using C++ and XILINX to improve the performance of SIMON and SPECK on ASICs, FPGAs, microcontrollers, and microprocessors. - Memory benchmarking via C code - Slice count benchmarking via FPGA - Gate equivalent benchmarking via ASIC Implementation

    $143 (Avg Bid)
    $143 Giá đặt trung bình
    5 lượt đặt giá
    Fpga setup Đã kết thúc left

    We are a high frequency trading startup based out of India and we are looking to setup an fpga based trading infrastructure

    $562 (Avg Bid)
    $562 Giá đặt trung bình
    8 lượt đặt giá

    Các bài viết top fpga cộng đồng