Mpsoc designcông việc
...device for the project. Intended Functionality: The main objective of this project is to develop a networking solution using Ethernet. The freelancer should be experienced in VHDL developments and in networking functionalities for Xilinx KCU116. Specific Requirements: - 1/2.5GB Axi Ethernet Core (not provided, but free trial is available by Xilinx) based - 1Gb speed required - No Microblaze or MPSoC, only VHDL code. - Configuration must be done by AXI-Lite bus (No Configuration vector) - Ethernet frames must be sent by AXI-Stream bus - Reference ISE is Vivado 2022.1 ISE Milestone: A simple example which send Ethernet packets on KCU116. Project Operating will be verified by connecting a PC with wireshark in order to receive the sent frames. If you have the required skills and ...
I am looking for an experienced Altium PCB design who has worked on complex PCB design using Altium 365. - Zynq ultrasclae+ MPSoc FPGA - AD9361 - AD9371 I only need individual freelancer. Full-time available can work on US time zone should reply ASAP. Please share your portfolios what you have done in similar fields.
I am looking someone having experience with MIPI CSI-2 TX (FPGA to other device, not the MIPI-CSI2 Camera into FPGA) on Xilinx MPSoC Platform and Petalinux. Its a consultation and/or development project. Anyone having experience with MIPI-CSI2 TX with any embedded Linux (ARM or other embedded platforms) can also contact me here at Project. It is moreover embedded Linux driver development work based on MPSoC FPGA.
The project is to develop an application based on FPGA development board with interfacing Analog Eval. board for processing audio signal. Here is details : H/W will be used : 1- Zynq Zedboard or MPSOC development board. 2- AD7134 dual chip AD Development board. Both boards connected by FMC LPC/HPC connector. S/W - F/W : 1- AD7134 is supported by AD and it has all firmware required to interface to many fpga board, so we can use this ready HDL/DRIVER for interfacing the AD7134 to our fpga board. 2- interfacing to PC through Ethernet with ready library "LIBIIO" or using "Matlab FPGA data capture". We have all hardware development boards on hand, can use it remotely. Any details will be discussed in details.
...petalinux environment who able to support and guide me when I need some help (like now) or some theoretical / technical questions will popped up. This session is going to be for at least a few months, so I’d like to share with you one of my challenges and see if its fit to you. My current project: Bringing up on my custom board a Linux Image, my custom board very similar to the ZCU 106 Ultrascale+ MPSoC board. What I've already achieved: I’ve generated the which contains: fsbl, uboot, bl31, pmufw, , u-boot and image.ub. When I program the flash with this the start running, but than an Error occurred: [ 4.421147] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(179,2) [ 4.429576] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4
Hi! I want to deploy a custom RISC-V processor on FPGA. There are two tasks: 1. Deploy the core to run C codes on it and blink an LED (the core is implemented in Verilog and synthesizable). 2. Boot Linux Kernel (files are ready). I want to deploy the processors on the ZCU102 Zynq MPSoC Board (Zynq UltraScale) FPGA.
Hi! I want to deploy a Bluespec RISC-V processor on FPGA and run C codes on it. There are two cores I am interested in: Piccolo and Flute, both available on GitHub. I want to deploy the processors on the Arty A7 Board (Artix-7) and ZCU102 Zynq MPSoC Board (Zynq UltraScale) FPGAs. At the moment, I was able to synthesise, implement and upload the bitstream to the FPGA. However, I need help to link the software to the hardware and run C codes on it, such as printing a hello word string on UART (ELF files can be generated using the RISC-V GNU Toolchain). The hardware IP Cores are shown in the attached image (for Vivado). Now, I need to run C codes in it, and I need help with that part.
I have a board with XCZU2EG-SFVA625-1-i, I want the correct DDR configuration for the below DDR in Vivado 2019.1 MPSoC block: (One DDR only) AS4C512M8D4-83BCN
