Verilog vhdlcông việc

Bộ lọc

Tìm kiếm gần đây của tôi
Lọc theo:
Ngân sách
đến
đến
đến
Loại
Nhiều kỹ năng
Ngôn ngữ
    Tình trạng công việc
    4,669 verilog vhdl công việc được tìm thấy, giá theo USD

    cần code verilog theo bài báo này

    $62 (Avg Bid)
    $62 Giá đặt trung bình
    4 lượt đặt giá
    Viết bài tập Verilog Đã kết thúc left

    Viết Inverse kinematics chạy trên FPGA của Xilinx

    $2 - $8 / hr
    $2 - $8 / hr
    0 lượt đặt giá

    Hi Hassan Shahid, I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $600 (Avg Bid)
    $600 Giá đặt trung bình
    1 lượt đặt giá

    DO-254 Project - Task - Lint and Code coverage

    $184 (Avg Bid)
    $184 Giá đặt trung bình
    1 lượt đặt giá

    I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

    $68 (Avg Bid)
    $68 Giá đặt trung bình
    7 lượt đặt giá

    Image processing digital electronic system

    $312 (Avg Bid)
    $312 Giá đặt trung bình
    10 lượt đặt giá

    Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

    $149 (Avg Bid)
    $149 Giá đặt trung bình
    45 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $55 (Avg Bid)
    $55 Giá đặt trung bình
    1 lượt đặt giá

    ...generator, where scanline parameters are passed as input wires : scanline color, scanline thickness, scanline interval 5. output is overlayed by the bitmap OSD with the same resolution as output format Requirements : aside from the DDR memory interface, or PLL no vendor or encrypted IP blocks can be used, for example no Altera/Intel video pipeline. Everything must be in written verilog source code. Must include verilog testbench that will accept input picture(in any format) and produce resulting picture(in any format). suggested pipeline i/o ports: Sysclk, [23:0] RGBin, HSin,VSin,DEin, Clkin [23:0] RGBout, HSout, VSout, DEout, Clkout [31:0] parameters[0:...] (whatever count is required). all needed memory interfaces signals to the memory multiplexer. Any dev board an...

    $2000 (Avg Bid)
    NDA
    $2000 Giá đặt trung bình
    1 lượt đặt giá

    we have to give input images for that it should create a eigen face by using eigen values and eigen vectors and compare it with the given image matching or not in verilog so that I wanted to implement in the FPGA board I want it in gate level model

    $141 (Avg Bid)
    $141 Giá đặt trung bình
    5 lượt đặt giá

    I am looking to hire an individual who really understand this subject. should be able to solve any problems related to this subject. communicate and be able to write good programming and simulation designs.

    $143 (Avg Bid)
    $143 Giá đặt trung bình
    19 lượt đặt giá

    ...create a verilog code for image dehazing. The image is converted into a text file using Matlab(all pixel values are converted into corresponding hexadecimal values). This text file is given as the input to the verilog program. First we need to find the minimum of RGB value of each pixel and create a matrix. Then we need to consider a small window/mask in the new matrix and find the minimum of that mask and sweep the mask through the entire new matrix to create the darkchannel image. Then by using the equations using the darkchannel prior algorithm we need to recreate a haze free image. (the output of the verilog code will be a text file and is recreated into an image using Matlab. I am attaching a reference paper. I just need to get the basic dehazing part fro...

    $108 (Avg Bid)
    $108 Giá đặt trung bình
    6 lượt đặt giá
    Aparat de cafea in VHDL Đã kết thúc left

    Crearea unui aparat de cafea in VHDL(rulabil in programul Vivado) intr-un limbaj cat mai simplist indeplinind cerintele din documentul atasat.

    $8 (Avg Bid)
    $8 Giá đặt trung bình
    3 lượt đặt giá
    line following bot Đã kết thúc left

    I need code for my bot who follow the given line using line sensor. this code should be written in verilog language and fpga cyclone 4 is used as board.

    $14 (Avg Bid)
    $14 Giá đặt trung bình
    4 lượt đặt giá

    dark channel prior basically computes the minimum of rgb values present in a single pixel and assigns that value to the pixels. Once that is done, a patch of pixels is taken and the minimum is taken after which all the pixels in that patch are assigned the new minimum value. The input is a hex file of coloumn form and output is another hex file

    $101 (Avg Bid)
    $101 Giá đặt trung bình
    5 lượt đặt giá

    ...picture with excessively large, slow, power hungry designs. Researchers presented dozens of papers on how to make this better, completely missing the mark. This is your chance to get it right. Read this paper , then and look at their Verilog here to get a good understanding about state of the art FPGA BTC mining with verilog. Then apply that to YOUR FORK of the old standard in with an updated proxy for getwork. Clues follow to make FPGA BTC mining faster, smaller, and lower power, so that you will have REAL bragging rights for the fastest, smallest, lowest power FGPA miners. Goal >10x speed up

    $625 (Avg Bid)
    Nổi bật Bảo đảm Niêm phong Cuộc thi hàng đầu
    $625
    12 bài tham dự
    INTERVIEW PREPARATION GUIDE ! Đã kết thúc left

    I am a verification engineer in Bangalore India, and preparing for Top Semiconductor Companies Interview Process like INTEL, NVIDIA , GOOGLE , Qualcomm, NXP Semiconductors , SAMSUNG and many more etc. So I am looking for a verification expert ...showcase me your skills . So that after gaining knowledge with your help I can crack any company interviews . I want all types of problem solving questions to be covered including puzzles as well . Kindly ping me here if you help me out with above . Kindly provide all types of possible questions which a company can ask in a interview , I need a kind of Question Bank. Mandatory Skills : Verilog , System Verilog, UVM , Functional Coverage , Code Coverage , Assertions , Constraints , Digital Electronics and FSM problem Solving questi...

    $2430 (Avg Bid)
    $2430 Giá đặt trung bình
    1 lượt đặt giá

    ...this project students are asked to implement a an XTEA Encryption/Decryption VHDL Engine, implemented in both C code and VHDL code. It supposed to be built as a custom hardware module and be interfaced to the NIOS II soft processor in the Alter- Intel Cyclone V FPGA chip [De-10Nano board]. The HDL code implements 2 number of pins: first an input from stdr_logic_vector type form of 32-bit length, and second an output with 32-bit of the same type. The Key is 32-bit in length, and they must be stored inside the VHDL code. The input reception and output generation may take multiple clock cycles or states but could be designed in less than that if was applicable. The internet could be surfed to lookup codes for both C and VHDL but the group is responsible to conve...

    $479 (Avg Bid)
    $479 Giá đặt trung bình
    18 lượt đặt giá
    Vhdl projects Đã kết thúc left

    The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry,

    $45 (Avg Bid)
    $45 Giá đặt trung bình
    11 lượt đặt giá
    Vhdl for video processing FPGA Đã kết thúc left

    We need a VHDL designer with expertise on video processing codec.

    $33 / hr (Avg Bid)
    $33 / hr Giá đặt trung bình
    18 lượt đặt giá
    Build verilog simulations Đã kết thúc left

    Two tasks based on verilog, serial adder and RTL for APB based protocol. More information will be shared later. Deadline - 2days[maximum] Price - 75AUD

    $79 (Avg Bid)
    $79 Giá đặt trung bình
    2 lượt đặt giá

    Hello can you help me with this project it’s going to be similar to lab 4 that I have attached. I have attached the project pdf too ( 193.22 KB) this one Division.c #include "system.h" #include "altera_avalon_pio_regs.h" #include <stdio.h> /* register offset definitions */ #define DVND_REG_OFT 0 // dividend register address offset #define DVSR_REG_OFT 1 // divisor register address offset #define STRT_REG_OFT 2 // start register address offset #define QUOT_REG_OFT 3 #define REMN_REG_OFT 4 #define REDY_REG_OFT 5 #define DONE_REG_OFT 6 /* main program */ int main () { alt_u32 a, b, q, r, ready, done; printf("Division accelerator test #2: nn"); while (1){ printf "Perform division a / b = q remainder rn"); printf("En...

    $623 (Avg Bid)
    $623 Giá đặt trung bình
    13 lượt đặt giá
    I need a Verilog/Vivado expert Đã kết thúc left

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    $39 (Avg Bid)
    $39 Giá đặt trung bình
    10 lượt đặt giá

    Im working on a Simon Says project that needs to be implemented on a Xillinx FPGA. It alsof includes memory, FSM

    $37 (Avg Bid)
    $37 Giá đặt trung bình
    3 lượt đặt giá
    System Design and VHDL expert Đã kết thúc left

    System Design and VHDL expert for urgent Task

    $8 / hr (Avg Bid)
    $8 / hr Giá đặt trung bình
    13 lượt đặt giá
    VHDL Project Đã kết thúc left

    The VHSIC Hardware Description Language (VHDL) is a hardware description language (HDL) that can model the behavior and structure of digital systems at multiple levels of abstraction, ranging from the system level down to that of logic gates, for design entry, documentation, and verification purposes. Since 1987, VHDL has been standardized by the Institute of Electrical and Electronics Engineers (IEEE) as IEEE Std 1076; the latest version of which is IEEE Std 1076-2019. To model analog and mixed-signal systems, an IEEE-standardized HDL based on VHDL called VHDL-AMS (officially IEEE 1076.1) has been developed.

    $20 (Avg Bid)
    $20 Giá đặt trung bình
    4 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $35 / hr (Avg Bid)
    $35 / hr Giá đặt trung bình
    1 lượt đặt giá
    I need vhdl code Đã kết thúc left

    1010 sequence dectectorwith 20 bit frame with consecutively 3 frames with 16 bit payload and 4 bit header

    $13 / hr (Avg Bid)
    $13 / hr Giá đặt trung bình
    6 lượt đặt giá
    Digital Verilog Time sensitive Đã kết thúc left

    1) Frequency divider by - / 2n - / by any integer 2) Serial Peripheral Interface (SPI) - Both master and slave 3) UART TX/RX - Asynchronous serial communication - Start bit, Stop bit, over sampling etc. - Exercise on cross-clock domain synchronizer What to submit - RTL code (.v) with inline comment - Test bench (.v) with inline comment - Timing diagram (gtkwave) with annotation - Rough description of the corresponding circuit Quick turnaround needed

    $34 (Avg Bid)
    $34 Giá đặt trung bình
    6 lượt đặt giá

    Hi Aamir Sohail N., I noticed your profile and would like to offer you my project. We can discuss any details over chat. It is another VHDL Project I need implemented

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    1 lượt đặt giá

    Need a System Verilog Expert for digital logic circuit design

    $16 (Avg Bid)
    $16 Giá đặt trung bình
    10 lượt đặt giá
    Need a C# and VHDL developer Đã kết thúc left

    The budget is $50. You will wire down a vhdl in Vivado to display 4 digit intiger on a display of basys3 board. The data will be arrived with a UART port. You can write down the UART or you can use a ready class. I can give you the model number when you are ready. You will load the image file by a c# program and send a 4 digit number to be displayed on the display. I need both vhdl code from vivado and c# code from visual studio. Thank you

    $106 (Avg Bid)
    $106 Giá đặt trung bình
    5 lượt đặt giá
    State Machine VHDL Đã kết thúc left

    Hi Daniel C., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    1 lượt đặt giá
    timing waveforms for vhdl code Đã kết thúc left

    I have vhdl code. i need timing waveform from modelsim .

    $28 (Avg Bid)
    $28 Giá đặt trung bình
    9 lượt đặt giá
    Project for Mohan V. Đã kết thúc left

    I have a VHDL project available. I have a file that uses "process" that we want to rewrite in purely structural VHDL using components such as D flip flops and latches. Are you available for this task?

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    1 lượt đặt giá
    Project for Sardar Hasnain A. Đã kết thúc left

    Hi Sardar Hasnain A., I have a VHDL project available. I have a file that uses "process" that we want to rewrite in purely structural VHDL using components such as D flip flops and latches. Are you available for this task?

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    1 lượt đặt giá
    Write VHDL code for Vivado Đã kết thúc left

    I have a file in VHDL that I want to rewrite. The file uses "process" but we want to rewrite it using components. We have some of the modules you could use already written.

    $50 (Avg Bid)
    $50 Giá đặt trung bình
    5 lượt đặt giá
    Verilog programming Đã kết thúc left

    Multicycle Processor Controller

    $555 (Avg Bid)
    $555 Giá đặt trung bình
    20 lượt đặt giá
    Verilog Coding Đã kết thúc left

    We need to program a FPGA board using verilog code with XNOR, Multiply, shiftleft and add modules that can run on the board using different switches. When we compile the code there are no errors but when we try to put the code onto the board it is showing only zeros so we think that there is something wrong with the XNOR, Mul, shiftleft or ADD modules. I will attach all codes and the manual for the project below, thanks.

    $49 (Avg Bid)
    $49 Giá đặt trung bình
    11 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $55 (Avg Bid)
    $55 Giá đặt trung bình
    1 lượt đặt giá
    Verilog circuit modelling Đã kết thúc left

    The entire description of the project is in the file below Circuit modeling in

    $188 (Avg Bid)
    $188 Giá đặt trung bình
    6 lượt đặt giá

    Write the equivalent VHDL code, and Verify the correct operation through Vivado Simulator by comparing your simulation results with those of MARS runs.

    $77 (Avg Bid)
    $77 Giá đặt trung bình
    4 lượt đặt giá

    Need to implement Pmod MAXSONAR on Arty A7-35T board

    $156 (Avg Bid)
    $156 Giá đặt trung bình
    4 lượt đặt giá

    I need to implement digital signature algorithm in Xilinx Vivado Design Suite using Verilog. Please find the attachment for complete details of project.

    $292 (Avg Bid)
    $292 Giá đặt trung bình
    4 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    1 lượt đặt giá

    I want to create programming routines to be recorded on an FPGA

    $33 / hr (Avg Bid)
    $33 / hr Giá đặt trung bình
    15 lượt đặt giá

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    $32 (Avg Bid)
    $32 Giá đặt trung bình
    5 lượt đặt giá

    Hi Moaz Khaled Feriz K., I noticed your profile and would like to offer you my project. We can discuss any details over chat.

    $16 / hr (Avg Bid)
    $16 / hr Giá đặt trung bình
    1 lượt đặt giá

    Project to be done in VHDL, so I am looking for an expert. The objective is to create a testbench for one circuit, and simulate the a few operations including storing data in it as well as retrieving data from it. I can share more details in PM.

    $39 (Avg Bid)
    $39 Giá đặt trung bình
    6 lượt đặt giá
    servomotor in vhdl Đã kết thúc left

    separate project in 3rd part, first make the chdl codes according to the state machine as well as their test ban (Reception and emission), make a top entity etc...

    $43 (Avg Bid)
    $43 Giá đặt trung bình
    5 lượt đặt giá