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    3,854 verilog vhdl công việc được tìm thấy, giá USD
    Viết bài tập Verilog Đã kết thúc left

    Viết Inverse kinematics chạy trên FPGA của Xilinx

    $2 - $8 / hr
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    0 lượt đặt giá

    I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

    $509 (Avg Bid)
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    VHDL Expert needed -- 4 6 ngày left
    ĐÃ XÁC THỰC

    communication between two usarts

    $111 (Avg Bid)
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    2 lượt đặt giá

    I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max

    $112 (Avg Bid)
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    12 lượt đặt giá
    Xilinx FPGA Projct 3 ngày left
    ĐÃ XÁC THỰC

    The Project is to develop Verilog code to control DDR4 DRAMs via a Memory Controller and I2C interface using a Xilinx Zync+ UltraScale FPGA.

    $10000 (Avg Bid)
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    1 lượt đặt giá

    I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

    $56 (Avg Bid)
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    4 lượt đặt giá
    VHDL Expert needed 4 ngày left
    ĐÃ XÁC THỰC

    I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.

    $30 (Avg Bid)
    $30 Giá đặt trung bình
    3 lượt đặt giá

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $50 (Avg Bid)
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    1 lượt đặt giá

    By using quartus ii, i have to meet the specifications of the report, by implementing the designs given and using hdl verilog, check the design.

    $120 (Avg Bid)
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    3 lượt đặt giá

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $12 / hr (Avg Bid)
    $12 / hr Giá đặt trung bình
    2 lượt đặt giá

    need VHDL code expert .........

    $21 (Avg Bid)
    $21 Giá đặt trung bình
    7 lượt đặt giá

    Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

    $145 (Avg Bid)
    $145 Giá đặt trung bình
    5 lượt đặt giá

    Looking for VLSI experts having strong digital electronics and verilog concepts

    $79 (Avg Bid)
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    8 lượt đặt giá
    simple snake fpga 2 ngày left

    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

    $6 / hr (Avg Bid)
    $6 / hr Giá đặt trung bình
    4 lượt đặt giá

    design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

    $164 (Avg Bid)
    $164 Giá đặt trung bình
    14 lượt đặt giá

    Hi nikafanasnikafan, I noticed your profile and would like to offer you my project in VHDL. We can discuss any details over chat.

    $50 (Avg Bid)
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    1 lượt đặt giá

    I want implementation of AHB protocol using one master three slave architecture in Sytem verilog (test bench with generator, driver,monitor, scoreboard)

    $8 (Avg Bid)
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    1 lượt đặt giá

    we need help for a project , please contact me

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    Lock In amplifier 1 ngày left

    I want to built a digital lock in amplifier. I prefer to use VHDL and spartan3E board for the project. it will give the depth idea of phase locked loop, direct digital synthesis.

    $79 (Avg Bid)
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    Vhdl project Đã kết thúc left

    Vhdl very small project, 8 bit alu

    $28 (Avg Bid)
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    In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. You have to implement the game of pong. One palette should be operated by the user with the help of buttons, and the other should be controlled by the computer. To be able to view the score.

    $13 / hr (Avg Bid)
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    I want locate any transmitter with time differnece of arrival method and hyperbolic navigation I already did with sdr but its too far away from real time and does not usable that`s why i want to try on fpga for high speed.I am new in fpga and I need help

    $998 (Avg Bid)
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    Build 3 small tasks in Verilog Đã kết thúc left

    I need help with building 3 tasks in Verilog. I can release the milestone only after that I check that the task you send me is 100% working (something like 7 days from the send time).

    $28 (Avg Bid)
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    experts in the field of Verilog Code writing in Xilinx, behavioral level HDL

    $23 (Avg Bid)
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    Line Folower Robot verilog code Đã kết thúc left

    We are making Line follower Robot using a line sensor, motor Driver(L9110s) and FPGA board(De-0 nano board). For this purpose, we want someone to write a code in Verilog language for the line sensor to communicate to FPGA and motor Driver

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    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
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    1 lượt đặt giá

    Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

    $301 (Avg Bid)
    $301 Giá đặt trung bình
    1 lượt đặt giá
    build me a Verilog code -- 2 Đã kết thúc left

    Design a counter using Verilog that will count up until your last 4 digit in your student ID using cascading counters. For an example if your last 4 digits of your ID is 3025, then your counter will count until 3025 ms.

    $20 (Avg Bid)
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    9 lượt đặt giá

    big team required Coin expert+ VHDL developer+ FPGA expert at least a coin expert and VHDL developer

    $2812 (Avg Bid)
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    4 lượt đặt giá
    Project for Shai K. Đã kết thúc left

    Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

    $301 (Avg Bid)
    $301 Giá đặt trung bình
    1 lượt đặt giá
    Project for Junaid A. Đã kết thúc left

    Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

    $308 (Avg Bid)
    $308 Giá đặt trung bình
    1 lượt đặt giá

    Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

    $500 (Avg Bid)
    $500 Giá đặt trung bình
    4 lượt đặt giá
    build me a verilog code Đã kết thúc left

    Using Verilog code Design a subway entrance turnstile that limits the number of people enter for an example only 5 people allowed to enter and the gate will close and open again if the number of people lesser than 5.

    $24 (Avg Bid)
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    Verilog HDL -- 2 Đã kết thúc left

    design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL.

    $32 (Avg Bid)
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    5 lượt đặt giá
    Verilog HDL Đã kết thúc left

    design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL.

    $67 (Avg Bid)
    $67 Giá đặt trung bình
    3 lượt đặt giá

    I need help with building 3 tasks in Verilog and need help to fix 2 tasks. Simple tasks. I can release the milestone only after that I check that the task you send me is 100% working (something like 7 days from the send time).

    $23 (Avg Bid)
    $23 Giá đặt trung bình
    5 lượt đặt giá
    digital design Đã kết thúc left

    You will design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL

    $42 (Avg Bid)
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    10 lượt đặt giá

    Xilinx FPGA-based implementation of the parameterized delay line with good resolution, say in steps of 10ps and good delay range say 512 steps and with minimum FPGA resources say less than 2% utilization. Deliverables 1. RTL code in Verilog/SV/VHDL and Xilinx Syntheis scripts 2. TB and Verification environment (with parameters) and results 3. Documentation with Architecture Diagram, Algorith...

    $424 (Avg Bid)
    $424 Giá đặt trung bình
    11 lượt đặt giá

    Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

    $546 (Avg Bid)
    $546 Giá đặt trung bình
    6 lượt đặt giá
    ARM MicroProcessor programming Đã kết thúc left

    by using VHDL and software Modelsim i need code and simulation of ARM microprocessor architecture

    $152 (Avg Bid)
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    UART transmitter Requirements for the Task:- 1:-Code should be based on FSM 2:-Baud Rate should be 115200 3:-Message Transmitted by the UART like this “AB-C-DE-#” 4:-This code should work properly in FPGA board . 5:-There should be three input port in code Suppose : Input A,B,C If A value is high message should be “AB-C-DE-#” If B value is high message should be “FG-...

    $28 (Avg Bid)
    $28 Giá đặt trung bình
    4 lượt đặt giá
    Frame Buffer Đã kết thúc left

    Develop VHDL IPs for high speed read and write to DDR for image processing applications for NIOS based SoC designs

    $20 / hr (Avg Bid)
    $20 / hr Giá đặt trung bình
    3 lượt đặt giá

    I did a project on modelsim, I could not write the testbench properly, I need some help to figure out what I did wrong. The code is about 100-200 lines, test bench is about 50 lines. It takes approximately 1-2 hours max.

    $22 (Avg Bid)
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    5 lượt đặt giá

    My project coding will be in verilog hdl on xilinx vivado. So i need coding help. I will send you circuit design.

    $129 (Avg Bid)
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    8 lượt đặt giá

    I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

    $21 / hr (Avg Bid)
    $21 / hr Giá đặt trung bình
    10 lượt đặt giá

    I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with you and...

    $250 (Avg Bid)
    $250 Giá đặt trung bình
    1 lượt đặt giá
    Project for Majid A. Đã kết thúc left

    I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with yo...

    $250 (Avg Bid)
    $250 Giá đặt trung bình
    1 lượt đặt giá

    Verification using system verilog and uvm

    $159 (Avg Bid)
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    3 lượt đặt giá
    Advance digital system Đã kết thúc left

    I just need some with a high knowledge in Verilog

    $22 (Avg Bid)
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    6 lượt đặt giá