Verilog vhdlcông việc

Viết Inverse kinematics chạy trên FPGA của Xilinx

I have one zed board with ethernet on it. I one to display the output of the adder over the ethernet. Adder is not an issue you can download it from anywhere, should be in VHDL, then the output of the adder should be transferred to the ethernet and then use the telnet or putty to display the Output.

communication between two usarts

I need vhdl code for uart to be implemented on basys 3 my budget is 150 usd max

The Project is to develop Verilog code to control DDR4 DRAMs via a Memory Controller and I2C interface using a Xilinx Zync+ UltraScale FPGA.

I need a VHDL code of LVDS transmission between two FPGA`s. It is a 4 lane LVDS operating at 833.33MHz to transfer information from USART of 1st FPGA to USART of 2nd FPGA.

I need to write VHDL code for LVDS transmission between two FPGAs. Please ping me if you are familiar with this.

Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

By using quartus ii, i have to meet the specifications of the report, by implementing the designs given and using hdl verilog, check the design.

Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

need VHDL code expert .........

Using the VHDL, design and implement the chips for data compression and data decompression shown in the following figure. The data compression chip will be implemented in the satellite to compress the data received from the telemetry subsystem in the satellite to reduce the communication time with the ground station. The data decompression chip will be implemented in the ground station in order to...

Looking for VLSI experts having strong digital electronics and verilog concepts

design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

design very simple basic snake game in quartus. Provide me with the verilog code ,state diagram, design schematic, all codes and instructions for self implementation.

Hi nikafanasnikafan, I noticed your profile and would like to offer you my project in VHDL. We can discuss any details over chat.

I want implementation of AHB protocol using one master three slave architecture in Sytem verilog (test bench with generator, driver,monitor, scoreboard)

we need help for a project , please contact me

I want to built a digital lock in amplifier. I prefer to use VHDL and spartan3E board for the project. it will give the depth idea of phase locked loop, direct digital synthesis.

Vhdl very small project, 8 bit alu

In this project, a simple VGA (Video Graphics Array) controller shall be implemented using an FPGA Basys3. You have to implement the game of pong. One palette should be operated by the user with the help of buttons, and the other should be controlled by the computer. To be able to view the score.

I want locate any transmitter with time differnece of arrival method and hyperbolic navigation I already did with sdr but its too far away from real time and does not usable that`s why i want to try on fpga for high speed.I am new in fpga and I need help

I need help with building 3 tasks in Verilog. I can release the milestone only after that I check that the task you send me is 100% working (something like 7 days from the send time).

experts in the field of Verilog Code writing in Xilinx, behavioral level HDL

We are making Line follower Robot using a line sensor, motor Driver(L9110s) and FPGA board(De-0 nano board). For this purpose, we want someone to write a code in Verilog language for the line sensor to communicate to FPGA and motor Driver

Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

Добрый день Вы можете нам помочь с кодом vhdl cyclone 10 FPGA в программе Quartus Prime

Design a counter using Verilog that will count up until your last 4 digit in your student ID using cascading counters. For an example if your last 4 digits of your ID is 3025, then your counter will count until 3025 ms.

big team required Coin expert+ VHDL developer+ FPGA expert at least a coin expert and VHDL developer

Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

Hi, We need some helps with the VHDL code. We use CYC1000-with-Cyclone-10-FPGA do you have time?

Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

Using Verilog code Design a subway entrance turnstile that limits the number of people enter for an example only 5 people allowed to enter and the gate will close and open again if the number of people lesser than 5.

Vhdl code

design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL.

design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL.

I need help with building 3 tasks in Verilog and need help to fix 2 tasks. Simple tasks. I can release the milestone only after that I check that the task you send me is 100% working (something like 7 days from the send time).

You will design a sequential circuit for a simple two-sided telephone conversation and implement it using Verilog HDL

Xilinx FPGA-based implementation of the parameterized delay line with good resolution, say in steps of 10ps and good delay range say 512 steps and with minimum FPGA resources say less than 2% utilization. Deliverables 1. RTL code in Verilog/SV/VHDL and Xilinx Syntheis scripts 2. TB and Verification environment (with parameters) and results 3. Documentation with Architecture Diagram, Algorith...

Looking for a developer willing to create bitstreams for FPGA crypto mining. Looking for a reliable dev with good experience. If you believe you fit the profile, pls apply. We are looking for serious candidates only.

by using VHDL and software Modelsim i need code and simulation of ARM microprocessor architecture

UART transmitter Requirements for the Task:- 1:-Code should be based on FSM 2:-Baud Rate should be 115200 3:-Message Transmitted by the UART like this “AB-C-DE-#” 4:-This code should work properly in FPGA board . 5:-There should be three input port in code Suppose : Input A,B,C If A value is high message should be “AB-C-DE-#” If B value is high message should be “FG-...

Develop VHDL IPs for high speed read and write to DDR for image processing applications for NIOS based SoC designs

I did a project on modelsim, I could not write the testbench properly, I need some help to figure out what I did wrong. The code is about 100-200 lines, test bench is about 50 lines. It takes approximately 1-2 hours max.

My project coding will be in verilog hdl on xilinx vivado. So i need coding help. I will send you circuit design.

I'm looking for a FPGA Firmware engineer who has rich experience in FPGA and VHDL/verilog programming. The right candidate should have an experience in Matlab and HDL Coder. The board is Zynq FPGA controller. The project is to implemente a Xilinx partial reconfiguration model for an SDR on the AD9361-Z7035 with ADRV1CRR-BOB. Also should have telecommunication knowledge. Please bid with the ...

I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with you and...

I have a board with a Xilinx FPGA programmed in VHDL using Xilinx ISE Design Site 14.7 . The FPGA performs many functions on the board address decode frequency counting, totalizing, latch logic and quadrature decode etc. We need this part of the project debugged or rewritten. I want to know if you would like to accept this project on a fixed cost basis. If so I will share the project with yo...

Verification using system verilog and uvm

I just need some with a high knowledge in Verilog