ST25R3916B-Based NFC Antenna Array – Review, Redesign & Prototype

PROJECT SUMMARY: I need an experienced RF/NFC hardware engineer to design a compact, modular 4×4 NFC sensor array board. The board will be used to detect and identify NFC-tagged objects placed on a flat surface (e.g., industrial tray, logistics sorting grid, or interactive tabletop application). Multiple boards (up to 6) will be tiled together to cover larger surfaces. Each board must detect and report the UID of ISO 14443 and ISO 15693 NFC tags placed on any of its 16 positions, within 500ms scan time for the full array. This is not a greenfield project. I have an existing but non-functional 6-layer PCB design (EasyEDA source files available) that attempted this with an ST25R3916B, STM32L476, analog multiplexers, P-MOSFETs, and PIN diodes simultaneously. The design is overengineered and contains at least one confirmed routing error (VDD_D unconnected). I need an engineer who can: 1. Review the existing design and identify all issues 2. Propose a simplified, clean redesign 3. Execute the redesign through to tested prototype TECHNICAL REQUIREMENTS: Core Architecture: - NFC Reader: ST25R3916B-AQET (mandatory – I have stock) - Protocol: ISO 14443A/B and ISO 15693 - Antenna count: 8 crossed antennas (4 row + 4 column) covering 4×4 grid - Antenna switching: PIN diodes (e.g., BAR63-03W), NO analog multiplexers - MCU: STM32G0 or STM32L0 series, 48-pin package, cost-optimized - Power: Single LDO from 5V input, max 500mA - Communication: UART and/or SPI interface to external host controller - PCB: 6-layer, FR-4, JLCPCB-compatible, approx. 260×280mm - Detection distance: 1–3 cm through 1 cm substrate (wood or plastic) - Scan speed: All 16 positions scanned in < 500ms, target < 300ms Antenna Design: - Crossed antenna topology (row antennas + column antennas) - Individual LC matching network per antenna (2–3 passive components) - AAT (Automatic Antenna Tuning) of ST25R3916B used for fine adjustment - PIN diode switching via MCU GPIOs with bias resistor and DC blocking capacitor - No analog multiplexers (ADG706, CD74HC4067, or similar) in the RF path Expansion Provisions: - 4–6 spare GPIOs exposed on header for future peripheral integration - UART/SPI connector (JST or similar) for daisy-chaining to host controller - Single data pin for addressable LED strip (WS2812B) – optional, prepare footprint only Design Constraints: - Board must be tileable: connectors and electronics on ONE short edge only - No components in the antenna area (center of the board) - All components on one side preferred (single-side SMT assembly at JLCPCB) DELIVERABLES: Milestone 1 – Review & Architecture - Written review of existing design (I provide EasyEDA source files) - Identification of all design errors and unnecessary complexity - Proposed simplified block diagram - BOM cost estimate - Deadline: 1 week Milestone 2 – Schematic Design - Complete schematic in KiCad or EasyEDA Pro - Design review session (video call or detailed written review) - Preliminary BOM with JLCPCB/LCSC part availability check - Deadline: 2 weeks after M1 approval Milestone 3 – PCB Layout - Complete 6-layer PCB layout - DRC clean, JLCPCB design rules applied - Gerber files, BOM, and CPL (pick-and-place) files ready for order - Deadline: 2 weeks after M2 approval Milestone 4 – Prototype Test & Validation - I order PCBs and ship to you (or you order, I reimburse) - Firmware: basic scan routine that reads all 16 positions and outputs UIDs via UART - Firmware must be compatible with Arduino IDE (STM32duino core) – no CubeIDE/HAL dependency - Documented test results: detection rate per position, scan time, read distance - Minimum acceptance criteria: >95% detection rate at 2 cm distance - Deadline: 2 weeks after boards arrive Budget is negotiable based on your proposal. PCB manufacturing and shipping costs are separate and paid by me. WHAT I PROVIDE: - Complete EasyEDA source files of existing (non-functional) design for reference - ST25R3916B-AQET chips (I have stock, can ship to you) - ISO 14443 and ISO 15693 NFC tags for testing - Previous design documentation and lessons learned - Quick response time for reviews and feedback REQUIRED SKILLS & EXPERIENCE: Mandatory: - Proven experience with ST25R NFC reader family (ST25R3911B, ST25R3916, or ST25R3916B) - RF PCB design experience, specifically NFC antenna design at 13.56 MHz - PIN diode switching circuit design for antenna arrays Preferred: - STM32 firmware development, ideally with STM32duino (Arduino core for STM32) - Experience with JLCPCB SMT assembly process - KiCad or EasyEDA Pro (no Altium-only engineers please) SELECTION CRITERIA: Please include in your proposal: 1. A brief description of a previous NFC/RFID antenna project you completed 2. Your assessment: Is PIN diode switching the right approach for 8 antennas, or would you suggest an alternative? 3. Your estimate for total scan time of 16 positions with the ST25R3916B 4. Availability and timezone I will NOT select based on lowest price. I have been burned by cheap, fast promises before. I want a clean, minimal, working design. Quality over speed. IMPORTANT NOTES: - This project has a history of failed attempts with multiple freelancers. I am looking for a long-term engineering partner, not a one-off delivery. - The application is proprietary. NDA available if required. - I am technically literate (electronics hobbyist level) and will actively participate in design reviews. I am not looking for someone to "just handle it" – I want to understand every design decision. - Communication in English or German. Timeline: ~8 weeks | Location: Europe preferred (timezone compatibility)

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