CPLD Project - NAND Flash Interface Controller

Project goal: Help design and implement a NAND Flash memory interface for a CPLD that will interface between a high-performance MCU and a NAND Flash device. Details: The CPLD will connect to the MCU using SPI (SO,SI,CLK,CS) and a DMA enabled memory I/O port (16-bit) and the CPLD will interface with the NAND memory using standard control, address and data lines (CE#,WE#,RE#,AKE,CLE,DQS and DQ0-DQ15). The SPI will be used to setup the controller's configuration (timings, sync/async, initial 40-bit address, number of address cycles, X8 or X16 mode, etc.) and also issue the operation (read/write DQ). The CPLD will also need to be able to be configured to interface with either 1.8V or 3V NAND memory. A single pin supply (for the CPLD BANK) will be used. My current design uses a STM32F723ZET6 MCU and an LC4256V CPLD, but I am open to suggestions or possible hardware changes for the final design. I have already implemented a similar project in C that runs in a MCU, so the main goal of this project would be to migrate that into a CPLD for speed and efficiency. For development, I will ship a LC4256V development breakout board, TSOP-48 adapter with breakout NAND pins, and various X8/X16 NAND memory. The chosen coder can test using any MCU they are familiar with. Please note: I am only going to choose a developer who previous CPLD/FPGA experience. So if you place a bid, please read the project's entire description and post what previous expierence you have and with what type of parts/devices.