We have developed Grostl RTL code for Grostl hash. We need an expert to optimize the code so I will use less LUT in Xilinx FPGA. We use Xilinx VCU9P and the goal of this project is to reduce the LUT down to 21%.
The c code link is : [login to view URL]
The RTL code and spec. will be sent after the project is awarded.
Target FPGA : Xilinx UltraScale+ XCVU9P
Target utilization : 21% of LUT
15 freelancer đang chào giá trung bình $2580 cho công việc này
Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 6 years. Please let me know if the requirement is still there I can work on it. Thanks.
Hi, Greetings!! We have huge experience of optimizing the code. Please chat with us so that we can discuss further Looking forward to your response Thanks & Regards, Suhasini