I am looking to create a receive-only UART-based interface to an LED driver chip (data sheet attached) that is part of a multi-drop network. Here are the basic functions it must perform:
-Operate on a Xilinx Cool-Runner CPLD or perhaps an Altera Max 3000 CPLD. The platform requires a low pin count, low-cost logic device. Xilinx highly preferred as I have a development board based on the XC2C128.
-Receive high-speed (10-20Mbps) serial data into a UART that can also detect a break signal. Xilinx provides HDL for this already on their website.
-Upon receiving a break signal, reset the comms interface to respond to an 8-bit address word. If the subsequent word does not match the local address, ignore all further traffic.
-Upon receiving a break, and if there is an address match, forward data words to LED driver using SPI until next break sequence.
-The first forwarded data in any data frame is a configuration byte and requires a special clock/data toggle scheme, see datasheet.
-Spit out a 16MHz clock signal to drive the LED driver's greyscale clock input.
-At every 128+1 clocks from the 16MHz signal, enable 1 of 8 row selects to engage the next LED matrix scan row, looping back to the first row when passing beyond row 8. Row select is ground-true.
-All GPIO used should be configured as open-collector.
I want to use the language you believe will use the fewest macrocells because we will only have a maximum of 64 macrocells. Please let me know if you think this is not possible. I find Verilog easier to read. =]