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Cadence Virtuoso Integrated Circuit ASIC

Based on my documents, I want you to have my past university student electronic circuit design and simulation project reproduced in Cadence Virtuoso.

It is a minimalist project, about 5 parts.

You should have knowledge of Cadence Virtuoso 6 software.

The electrical circuit in Cadence Virtuoso is using 350 nm (0.35um) Technology design kit.

The schematics, simulations, and layout will be provided once the job is finished.

Required to have strong experience in block-level designs, top level integration and Floorplanning , along with deep understanding of layout techniques.

Design rules, ESD, isolation, device matching and low parasitic.

A solid track record in full chip assembly and verification and cadence skill programming is a plus.

Producing and delivering high quality layouts .

Floorplanning, block level layout, top level integration and pad ring layout of RF/high speed blocks.

Coordinating layouts block resources and support other team members.

Conducting tape-out verification tasks which include: DRC, ANT, DUM and LVS.

Preparing technical reviews and product documentation.

Working with cross functional teams to deliver IC Products.

Kĩ năng: Thiết kế vi mạch, Kĩ thuật điện, Điện tử, Vi điều khiển, PCB Layout

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Về Bên Thuê:
( 10 nhận xét ) Paris, France

ID dự án: #17012503

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Hello sir, I am an IC Mask layout Design Engineer. I have experience to work in TSMC 7/16/22/130/180 nm node. Also worked with NCSU PDK, ASAP7 PDK Cadence Virtuoso I have worked so far IC CAD 12.2,12.3 also Versio Thêm

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