I'm looking for an experienced SERDES engineer to design a SERDES PCS on ASIC. This PCS will be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver.
Your tasks are
1. Write the PCS RTL code
2. Provide a compatible GTH transceiver configuration/RTL.
3. Provide guidance on verification of the whole link channel.