BRAM-DDR-DAC C Update

@InWebTechno

Hello, I am Inweb Technologies, a seasoned Software Development expert with over a decade of experience. I have carefully reviewed your project requirements for updating the C files to pull COE data from BRAM, write it into DDR, and stream it out to the AD9361 DAC. With my expertise in digital marketing and web development, I specialize in building optimized websites and executing result-driven marketing campaigns. I am confident in delivering a professional solution that meets your specifications. I would love to discuss your project further in chat. Best regards, Raj

@servicedigi

With 4+ years in embedded systems and FPGA/SoC development, we specialize in Zynq-based designs, DMA transfers, and high-speed data streaming to DACs like the AD9361. We focus on minimal, precise modifications that maintain existing functionality while meeting tight timing requirements. For your BRAM ➜ DDR ➜ AD9361 DAC update, we’ll: Approach • Modify existing C functions to read COE data from BRAM, write to DDR, and stream to DAC • Ensure data integrity and real-time performance with no alteration to waveform • Maintain compatibility with Xilinx/ADI no-OS environment • Add inline comments on every change for clarity Deliverables – Updated C source files with comprehensive inline comments – Short summary file detailing changes and build/run instructions – Validation via simulation or hardware test confirming COE data reaches DAC accurately We’ve handled similar tasks involving Zynq BRAM/DDR DMA transfers and AD9361 streaming, so we can deliver quickly while preserving your current workflow and code stability.

@marcioazambujo

Hi, there. I am interested your project. Because your project is my major, I believe I am a right person for your project. I have hands-on experience with Zynq (PS–PL data paths), BRAM access, DMA transfers to DDR, and streaming data to the AD9361 DAC using the Xilinx/ADI no-OS environment. I understand the constraint of no major refactor and will only modify the existing functions so the flow cleanly becomes BRAM → DDR → AD9361 DAC, preserving real-time behavior and leaving the COE data unaltered. I am comfortable working with tight timing requirements and can turn this around quickly, with clear inline comments explaining every change. I will also provide a short build/run note and verify correct output either via simulation or hardware-side confirmation, depending on what you have available. I can start immediately and focus purely on making the existing pipeline work reliably end to end. I hope to hear from you. Thank you

@Sh4h11d

Hello, I’ve reviewed your requirement and this is a straightforward extension of your existing no-OS Zynq design. Since your single-tone waveform is already working, the task is simply to modify the current C functions so the data path becomes: BRAM (COE) → DDR → AD9361 DAC I’ll keep changes minimal (no refactor), ensure COE data is transferred unaltered in real time, and maintain full compatibility with the Xilinx/ADI no-OS environment. Deliverables: Updated C sources with inline comments on all changes Short summary file explaining what was modified and how to build/run Confirmation (simulation or hardware) that COE data reaches the DAC correctly I have hands-on experience with Zynq, BRAM/DDR transfers, DMA, and the AD9361 API, and can deliver this quickly.

@QuickMentor

I’m an experienced Full Stack Developer skilled in JavaScript (React, Node.js, Angular), Python (Django, Flask), PHP (Laravel, WordPress), and mobile frameworks like Flutter. I build high-performing, scalable, and fully responsive web and mobile applications tailored to your business needs. I ensure clean, efficient code and timely delivery. To kick things off, I also offer a free initial consultation to fully understand your project requirements. Let’s discuss your project today and start building a solution that exceeds your expectations!

@hennaz1

I am a perfect fit for your project, understanding the need for a clean, professional modification of existing C functions to enable a seamless, user-friendly data path from BRAM to DDR to the AD9361 DAC, preserving real-time, unaltered COE data flow under the Xilinx/ADI no-OS environment. With expertise in embedded C programming, Zynq architecture, BRAM and DMA transfers, and AD9361 integration, I ensure automated, efficient code updates with clear inline comments. While I am new to freelancer, I have tons of experience and have done other projects off site. I would love to chat more about your project! im willing to do it for less money but still best quality in exchange for a good review Regards, Henrux Faurie