are to design
determine whether a given input i
s a leap year
The year input consists of four BCD digits YO, YT, YH, YM (YearOnes, YearTens, YearHundreds,
). The output is a single bit LY (LeapYear)
is true if the given input year is a
leap year. The circuit
must work for any year after 1582.
adhere to the following interface:
module LeapYear(LY, YM, YH, YT, YO)
input [3:0] YM, YH
, YT, YO;
leap years if they are divisible
by four unless they are also divisible by one hundred and
not divisible by four hundred.
Design your circuit hierarchically
in behavioral dataflow style.
First, create two modules (and
for determining if a 2
digit BCD number is divisible by
IsZero for determining if
BCD digit is zero
Use a propagation delay of 10ns for
module you create.
to verify each
Then instantiate these modules
in your LeapYear module
to perform the leap year function.
Draw a schematic showing how the modules are used and interconnected.
You do not need to create your own testbench
for the LeapYear module
. There will be
posted on the course web site. You can download it and include it in your project.
This final report must include
A brief problem description
The problem your circuit solves
The project deliverables (exactly what you are gen
Approach/methodology (the steps you will take to solve the problem)
Timing diagram showing the complete simulation of your Divisible ByFour module
Timing diagram showing the complete simulation of your IsZero module
showing how your
result of compiling and simulating
your LeapYear module
with the provided testbench
(not the complete timing diagram)
Note: To receive better than a 70% score your
must not only work but be shown to work
through your testbench and timing diagrams. If you submit a non
, fail to
exhaustively verify it, or fail to include your verification results you
will lose 30 points.
a single zip file to D2L containing the following:
[url removed, login to view]
your project report with all design work (diagrams, truth tables, K
your Verilog source code for
the LeapYear module
your Verilog source code for the IsZero module
your Verilog source code for the IsZero testbench
your Verilog source code for the DivisibleByFour module
your Verilog source code for the DivisibleByFour
3 freelancer đang chào giá trung bình $52 cho công việc này
Hi I am an electrical engineer and a lecturer in a reputed university. I can do the job perfectly. I have read all the details and be assured that you will be delivered every thing to earn more than 70% percent marks.
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