# odesign a combinationallogic circuit

ECE 171

Fall 2015

Project 2

You

are to design

a

combinational logic

circuit

to

determine whether a given input i

s a leap year

.

The year input consists of four BCD digits YO, YT, YH, YM (YearOnes, YearTens, YearHundreds,

YearMille

n

nia

). The output is a single bit LY (LeapYear)

that

is true if the given input year is a

leap year. The circuit

must work for any year after 1582.

must

module LeapYear(LY, YM, YH, YT, YO)

;

input [3:0] YM, YH

, YT, YO;

output LY;

Years are

leap years if they are divisible

by four unless they are also divisible by one hundred and

not divisible by four hundred.

in behavioral dataflow style.

First, create two modules (and

verify them)

:

DivisibleByFour

for determining if a 2

-

digit BCD number is divisible by

four

IsZero for determining if

a

single

BCD digit is zero

Use a propagation delay of 10ns for

each

output in

each

module you create.

Write testbenches

to verify each

module.

Then instantiate these modules

to perform the leap year function.

Draw a schematic showing how the modules are used and interconnected.

You do not need to create your own testbench

for the LeapYear module

. There will be

one

This final report must include

1.

A brief problem description

a.

b.

Specific requirements

2.

The project deliverables (exactly what you are gen

erating)

3.

Approach/methodology (the steps you will take to solve the problem)

4.

work

5.

Timing diagram showing the complete simulation of your Divisible ByFour module

6.

Timing diagram showing the complete simulation of your IsZero module

7.

Timing

diagram

showing how your

LeapYear module

performed

for a

few

test cases

8.

Simulation

log

showing

the

result of compiling and simulating

with the provided testbench

(not the complete timing diagram)

Note: To receive better than a 70% score your

design

must not only work but be shown to work

through your testbench and timing diagrams. If you submit a non

-

working

design

, fail to

exhaustively verify it, or fail to include your verification results you

will lose 30 points.

Submit

by

ing

a single zip file to D2L containing the following:

your project report with all design work (diagrams, truth tables, K

-

maps) and

timing diagrams

leapyear.v

the LeapYear module

iszero.v

your Verilog source code for the IsZero module

iszerotb.v

your Verilog source code for the IsZero testbench

divbyfour.v

your Verilog source code for the DivisibleByFour module

divbyfourtb.v

your Verilog source code for the DivisibleByFour

Kĩ năng: Kĩ thuật

Về Bên Thuê:
( 86 nhận xét ) Nairobi, Kenya

ID dự án: #8974562

## 3 freelancer đang chào giá trung bình \$52 cho công việc này

pmishu20

\$20 USD trong 3 ngày
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4.3
shabbir11255

Hi I am an electrical engineer and a lecturer in a reputed university. I can do the job perfectly. I have read all the details and be assured that you will be delivered every thing to earn more than 70% percent marks.

\$100 USD trong 10 ngày
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elecengr42

I am an electrical engineer specialized in electronics and communication and also working as instructor in University.I have very good expertise in circuit designing , digital design, communication system etc. I am als Thêm

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vw1702486vw

i am interested in this project, please open chat to discuss further. <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

\$35 USD trong 2 ngày
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