I have a very simple Cadence schematic and layout I have designed of an XOR gate. For some reason the nest lists do not match in the LVS check. I cannot figure out this simple task because I am new to the process.
The layout cannot change but corrections can be applied and the entire schematic can change to make the proper corrections to match the layout.
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I have read your problem with Cadence and I am interested in fixing it. I have 7 years of experience in teaching Electrical Engineering courses in university. Contact me so we will discuss further. Regards,