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Implement RSA algorithm synthesized code (512 bit) in Verilog


I would like to implement RSA algorithm synthesized code in Verilog up to 512 bit of encryption.

- Encryption data output size can vary from 16-bit to 512 bits.

- Prime number generation: two random prime number generated through LFSR and should be

stored in FIFO

- For every iteration different public and private key pairs should be produced.

Kindly contact know if this can be done within 2 days of time frame. We can discuss about budget.



Kĩ năng: Kĩ thuật, FPGA, Verilog / VHDL

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Về Bên Thuê:
( 0 nhận xét ) India

ID dự án: #16362243

9 freelancer đang chào giá trung bình ₹6964 cho công việc này


A proposal has not yet been provided

₹27777 INR trong 2 ngày
(313 Nhận xét)

A proposal has not yet been provided

₹600 INR trong 3 ngày
(54 Nhận xét)
₹11666 INR trong 3 ngày
(13 Nhận xét)

A proposal has not yet been provided

₹11111 INR trong 14 ngày
(0 Nhận xét)

I am an experienced RTL designer in one of the product companies. I have good experience in building complex digital systems. Pls. consider my bud.

₹1300 INR trong 2 ngày
(0 Nhận xét)

Hey, I have an experience in cryptography and it seems doable in two days so please contact me for more details.

₹4444 INR trong 2 ngày
(0 Nhận xét)

I could locate 4h per day to work on this project. expert on Verilog design & FPGA. Available platform for testing & simualtion. Relevant Skills and Experience worked in large company, expertise in Verilog design for Thêm

₹2250 INR trong 2 ngày
(0 Nhận xét)

I am an expert in digital design let me do it

₹750 INR trong 2 ngày
(0 Nhận xét)

I work in system verilog and c++ in my daily job. So I can assure u to code in system verilog. Also i can explain u and giv some suggestions.

₹2777 INR trong 1 ngày
(0 Nhận xét)