MCU ADC FPGA Migration & Bring-Up

I am migrating a proven Cable Fault Locator from its legacy parts (LPC1788 + LTC2252 + Cyclone V) to a more economical stack and need a hands-on engineer who can steer the hardware all the way to a clean power-up. Current collateral • Complete Altium Designer schematics of the existing board • Reference firmware that already drives a 800 × 480 TFT, external SDRAM, Flash and the parallel ADC stream Target platform • MCU: NXP [login to view URL] RT1062 (any close RT family device is acceptable) • ADC: AD9214 on the same 12-bit parallel bus • FPGA: Intel Cyclone 10 LP 10CL006YE144C8G, programmed over JTAG with Quartus 18.1 through a USB Byte Blaster II Scope of work – Translate the legacy Altium sheets to the new silicon, preserving all high-speed routing constraints. – Verify clocking, power rails and pin muxing for the [login to view URL] RT and Cyclone 10 combo. – Hand-off updated Altium files, BoM and any design notes needed by our firmware team. – Drive the first-article bring-up: JTAG access, SDRAM memory test, LCD frame buffer check, ADC capture integrity and seamless data hand-off to the FPGA fabric. Acceptance The job is considered complete once the new board: 1. Boots the [login to view URL] RT at its rated frequency from external Flash and runs an SDRAM memory stress test for 24 h without error. 2. Streams at least 105 MSPS from the AD9214 into the Cyclone 10 and echoes sample packets over UART/SPI for validation. 3. Displays a full-colour test pattern on the 800 × 480 TFT driven directly by the MCU. All design files, test code snippets and bring-up logs stay with us at delivery so the firmware port can move ahead smoothly. If you have recently powered up an [login to view URL] RT board, pushed Quartus bitstreams into Cyclone 10 devices, or wrestled with high-speed ADC buses, your experience will slot right in.

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