Have several ways to effectively reduce sidelobe the ACAR.
In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal.
I want to do all the processing with one FPGA without using any other block like DDS.
There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for corresponding processing will be developed on FPGA.
Bonus-You can enable the necessary flexibility through matlab when a FIR filter is designed.
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Design engineer with experience in large scale complex FPGA based system design with practicing in Verilog, SystemVerilog Hardware description Languages and Programming C, C++, Python. Let's Discuss further.