Finalise the VHDL code and test bench. Prepare the final report. This MUST be consolidated into a single report for the overall task, but will clearly show the contributions of the various sub-tasks. The report should include at least the following items:
i. a complete functional description of the system. Also include a block diagram of your synthesized design
ii. a description of how the system has been mapped onto the board resources, including pin-outs and include a summary of the FPGA resources used.
iii. A discussion of the simulation rationale (i.e. what you were trying to achieve) and the results Â– annotated in a manner that makes is completely clear that you have achieved what you set out to achieve.
iv. A discussion of the results of the timing analysis. Discuss area and performance. Were there any timing constraints you had to meet? Would this require you to change the design in any way?
v. a discussion of the major issues (tradeoffs, constraints etc) which affected the translation of the design into the language syntax (the actual design file, the test bench file and annotated simulation results should be attached as an appendix).
vi. Some comments on the following issues:
Â§ Integration of the final design Â– how was it accomplished, what (non-technical) problems were faced, how did you deal with these.
Â§ Design tools Â– e.g. ease of use, flow, performance, etc.
Two Function Calculator
Design and synthesize a calculator on the DE-1 board that can add and subtract integers:
Interface to a small 12-key keypad
Interface to a standard VGA display
Enter numbers via the keypad.Â Use some buttons on the DE-1 to provide the Â‘+Â’, Â‘-Â‘and Â‘=Â’ functions.
Display entered numbers and the result on the VGA terminal.Â Monochrome and low resolution characters are all that is required.Â You will need to work out how to generate the necessary timing to display the characters, so that the VGA synchronizes correctly.
For checking purposes, the calculator will copy each keystroke via the RS232 serial port to a PC for display on a simple ASCII terminal display.
Target your design to the DE-1 board and demonstrate correct operation.Â A hierarchical design using a package and multiple components (total, display, change, serial, etc) is required. Include simulation waveforms demonstrating the correct functional operation of your machine.