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Write a code in Verilog for a CNN that is able to detect digits from MNIST databse

I need a working code in Verilog that is able to successfully simulate, synthesize and generate bitstream on Xilinx Vivado for FPGA. The code should be able to implement a Convolutional Neural Network and take as input weights and biases from a pretrained model in Python and then use them to identify the 28x28 pixel test image from a MNIST database. Whatever digit is identified by the code, relevant LED on the FPGA board should light up. For eg if the digit identified is a 2, then 2nd LED on the board should light up.

Kĩ năng: Python, Verilog / VHDL, FPGA, Machine Learning (ML), Thuật toán

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Về Bên Thuê:
( 1 Nhận xét ) Leicester, United Kingdom

ID dự án: #30125618

10 freelancer chào giá trung bình£217 cho công việc này


Hi. Hope you are doing well. I have read your project details and I am very interested in your project. As you can see on my profile, I have rich experience with Python and ML part. Please send me message and let's dis Thêm

£250 GBP trong 7 ngày
(11 Nhận xét)

Hello Hiring Manager, I read your job descriptions carefully, I am very interesting in your job of Write a code in Verilog for a CNN that is able to detect digits from MNIST databse I have the enough experience and goo Thêm

£250 GBP trong 15 ngày
(3 Nhận xét)

Hi! I'm 5 years experienced Data Scientist with theoretical and practical experience in Data Science, Machine Learning & Deep Learning ready to do your work in an efficient way with strong analytical and logical reason Thêm

£150 GBP trong 2 ngày
(15 Nhận xét)

Hi Hiring manager I am Data Scientist, Deep Learning, Machine Learning, Flask, Docker expert In my practice I developed for clients: * AI chat bot, algorithmic trading strategy * AI rating systems, analytics dash boa Thêm

£250 GBP trong 4 ngày
(8 Nhận xét)
(4 Nhận xét)

Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and othe Thêm

£250 GBP trong 15 ngày
(16 Nhận xét)

Hi, Dear Employer, I have read your job post carefully. I have over seven-plus years of experience at ✔python, ✔Algorithm✔java, and others. Please feel free, and you may award me the task, I'd be happy and can present Thêm

£100 GBP trong 2 ngày
(4 Nhận xét)
(5 Nhận xét)

Hey, Hope you are doing well. I am able to write a verilog HDL code for a CNN that can be implemented on FPGA board. I will give you verilog code and generated bitstream from Xilinx Vivado 2016.2 IDE Tool. Please have Thêm

£200 GBP trong 7 ngày
(7 Nhận xét)

Have done the same project before. It was a MNIST handwriting detection on FPGA and Verilog. I am interested in doing this for you. Except I don't accept the python part and the input for the hardware should be clarifi Thêm

£330 GBP trong 7 ngày
(0 Nhận xét)