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Verilog Ethernet Tx/Rx - Repost

I am running a big project and am currently time constrained to implement the Ethernet connection.

This is a fairly easy project for someone with expertise in Verilog. The deliverables are as follows

-Verilog code to run on a Spartan 6 Atlys Board - (xc6slx45)

-simulation time diagrams (more details will be given to the winner)

- The code should be able to transmit and receive data at 100mbs (1Gbps support would be nice but not a must)

-Support a multicasting protocol (In that if I wanted to send data to 3 recepients out of 5 in the network, I should be able to do it easily)

-Support for broadcasting (be able to make the system send the data to all recepients in the network when needed)

-there are existing IPcores that offer a starting point and I would suggest that they be used as time is critical here.

some cores that can be used are

[url removed, login to view]://[url removed, login to view],ethernet_tri_mode

[url removed, login to view]://[url removed, login to view],ethmac

[url removed, login to view]://[url removed, login to view]

The final code should offer me a way of changing the sender and receiver address and also of using fake test data

Be able to peform checksum and CRC error checks

I need this done in less than a week as I believe its not much work for someone who is good in verilog

Kĩ năng: Verilog / VHDL

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