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AES Encryption/Description with SHA256 key for zedboard

Given the Open Cores from the open cores project I want a simple module that is able to do the following on a Xilinx ZedBoard:

1. Given 256 bit BITKEY, scramble the input with a hard coded IDKEY in the FPGA and provide a AESKEY

2. The same response needs to be piped to an AES256 module from OPEN CORES in order to encrypt/decrypt a stream of data


1. 256 BITKEY

2. selector BIT for encrypt decrypt (the output needs an XOR for decrypt)

3. stream of data as 256 bit 'chunks'. The architecture here should be trivial to support a driver easily.


1. 256 AESKEY

2. stream of encrypted/decrypted data as 256 'chunks'


This should be the bulk of the work; There needs to be diagrams and specifications for reproduction on another ZedBoard. This should include:

1. Layout of blocks

2. FPGA registers used and how the driver should interact with them

3. Maximum bandwidth achieved

4. Tests that were executed to prove design and plots of the execution of these tests. A test suite should be present for both encryption and decryption with different IDKEY.

To expand on deliverable details:
The 'chunks' are smaller when being pipped in the AXI interface. The manner in which data is split up is up for efficiency is up to the designer.
AXI logic needs to be completed in order for a 32 bit Ubuntu Linux running on the zedboard to call the encryption, decryption on PL side.
There needs to be a driver implemented for the linux 32 bit for the two calls to go through in C++ code. The input for this function call should be the data that is being encrypted/encrypted in some type of buffered structure, the BITKEY, the bool selector BIT flag.

Kỹ năng: FPGA, Verilog / VHDL

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Mã Dự Án: #14856080

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$155 USD trong 15 ngày
(12 Đánh Giá)

6 freelancer đang chào giá trung bình $155 cho công việc này

$155 USD trong 3 ngày
(90 Đánh Giá)

I have experience with Zynq device and zedboard. I can take the core form opencore and develop any glue logic and ARM driver too Relevant Skills and Experience I have [url removed, login to view] from Germany and currently working as profess Thêm

$300 USD trong 3 ngày
(2 Đánh Giá)

Designed expertise in Verilog and Link Layer functions like scrambler, AES algorithm. Already have experience with the same.

$108 USD trong 4 ngày
(2 Đánh Giá)

I m 4+ years experienced in Fpga IP core development.I have also worked on AES and sha implementation in past.I have worked on platform Zynq 7000

$110 USD trong 10 ngày
(0 Đánh Giá)

already have done this project, ping me if you interested.

$99 USD trong 3 ngày
(0 Đánh Giá)