Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only)
I don't want imaginary freelancer, please.
14 freelancer đang chào giá trung bình $103 cho công việc này
Dear sir I have more than 10 years experience in digital design using vhdl and verilog, please check my profile also please message me so that we can discuss
Hi I designed similar project in verilog so I have the adequate knowledge. It's only programing language different. I knows both verilog and vhdl so I can do your work within time. Thanks
Hello, I am an Electrical Engineer and I want to look at your VHDL code and fix it. If I can fix it, you can assign me to the project. Otherwise, you lose nothing. Please contact me for details and discussion.
Hi, We are experienced with FPGA design in VHDL. It seems that you have already implemented the function using some algorithm and you need some fixing done in it. We can have a look and help you with it. Thank you
I have done lots of project with Fpga with VHDL language(face recognition, Tweedle factor, games, etc.) If you elaborate your code a little bit I can do the task you want easily. No imagination!:) Regards,
Hello, I have worked with FPGAs and I'm able to check your code, but I need more details of the requirements. Are there any timing requirements?, does it need to be pipelined?