I am a third-year student from the Department of Electronics and Electrical Communication Engineering at the Indian Institute of Technology, Kharagpur. This is the domain of my interest. I have more than 6 months of continuous experience of Verilog coding.
One of my last semester lab was completely on Verilog coding (VLSI Engineering). I am in great touch. You can test me if you want.
I shall be committed to my work. I shall readily acquaint myself with any pre-requisites needed for the project. I hope to be able to go beyond the problem statement and produce the quality of the research work required for the project. I request you to please consider.
Thank you.