I am a senior digital design engineer,
I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog.
I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC.Thêm
I am vhdl expert for digital hardware design in dsp, data path, arithmetic and communication related circuits. Recently i completed the project that are in those domains for free lancer. You can check my profile andThêm
I have experience in SDR and Matlab HW in the loop with Xilinx FPGA.
I proposed to run simulation in Matlab and the implement a test code with HDL coder.
After that the QPSK mod/demo could be optimized for the specificThêm