This project consists to port some c code (around 50 lines) to Verilog in order to run on a FPGA.
Output of the contest
Verilog .v source file equivalent of verilog.c
testbench .v file equivalent to doSimulation()
You can run the C code with "gcc main.c && ./[login to view URL]"
Elements to select the winning bidder:
- Partial screenshot of the implementation or snipset of the implementation
- Any ideas, comments, remarks how to get the best implementation
- How MIN2 and MAX2 is implemented
- Approximate number of LUTs of the module
- If a Lattice Diamond project is provided for the simulation. I use Lattice which is freely available at [login to view URL] (including the simulator)
- The code has been tested on a simulator (required)
- The code has been tested on a FPGA (optional)
- CV and resume of the bidder
7 freelancer đang chào giá trung bình $55 cho công việc này
Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss Best regards