ASICdesigner

Abstract I am a VLSI design professional with 3 Year experience in Front end Digital design/ Verification in TOP MNCs and 1 Year technical teaching and VHDL/VERILOG Projects experience. Technical Education Ø Undergone a Specialized Training course “Advanced Post Graduate Diploma in VLSI Design” from VEDANT, Semiconductor Complex Ltd, Mohali Ø B.E. in Electronics and Electrical Communication from Punjab Engineering College (P.E.C), Chandigarh Courses Attended Ø Certificate Course in “Nanotechnology: opportunities and challenges” at NITTTR, Sec 26, Chandigarh. Ø Certificate Course in “Matlab Based VLSI design” at NITTTR, Sec 26, Chandigarh. Skills :- Languages - VHDL ,Verilog , System Verilog and C Expertise Area - Digital design , Static Timing Analysis , Design implementation from scratch , Testbench Design and Verification, Basics of FPGA implementation, Mathematics and Analytical Reasoning Tools - Cadence-NCSim, Cadence - debussy, Xilinx-XST, ModelSim, Leonardo spectrum. Platforms - Linux, Solaris-Unix and Windows On chip bus protocols - AMBA (AHB) , On - chip debugger Communications - EPON , Ethernet packet processing – AES encryption/Decryption , Churning - Vendor specific encryption algorithm , MPEG Standards , Nexus protocols, DSP Filter design Experience Summary Ø 1st Feb 2009 Onwards, Working as a Faculty of VLSI, Digital electronics, Network Analysis and Control Systems and handling DSP/VLSI Lab and VHDL/VERILOG projects in electronics and communications department at DBE College, Punjab. Ø Jan 2007 to May 2008 ,worked as a "FSL Design Engineer 1" with Freescale Semiconductors Pvt. Ltd . Ø July 2005 to Jan 2007, worked as a " Design Engineer " with Conexant Systems (India) Pvt ltd Experience Details Company Project details Responsibility Freescale semiconductors On Chip debugger Block of Multi-core Chip Study of Nexus Standard, Test plan development, Test Bench design, Functional Verification and code coverage analysis of OCDI (block in On-chip debugger block) in System Verilog ( System Verilog Base class library ). The OCDI collects data traces, performance events and address traces from various On – chip devices and selects the appropriate device for debugging. Soc level coverage tool (Internal) setup Communication Engine of SOC Verification of Communication Engine Block. The protocols verified were HDLC, TDM, ATM , Bisync , Ethernet and some General test cases in VERA ( Vera Base class library ) 8382 Study of Video compression MPEG 4 standards. System Verilog Training. Project was dropped afterwards. Conexant Systems Broadband Ethernet based – GPON Chip Design and verification of 16 bit timing critical GPON Churning block consisting of 2 parallel running 8 bit churning engines from Scratch in Verilog and VHDL both. The block takes in 16 bit data, 24 bit key and gives out 16 bit churned (encrypted) data . Broadband Ethernet Based – EPON Chip Test plan development, Test bench design and Verification of 128-bit AES Encryption/decryption Engine in VHDL. The AES Block encrypts /decrypts the data received from EPON framer /PCS layer block of the chip .It supports NIPS – AES standard. It can work in various different modes depending on the Programming Broadband Ethernet based – EPON Chip Test bench module creation, Integration of test bench module and Verification of 8-bit Churning block in the AES block in VHDL EPON Chip Design of 8-bit to 32-bit converter in VHDL and Verilog EPON Chip Design of 3 consecutive F876 pattern’s detector in VHDL and Verilog Academic Projects Ø DSP Based Project – FIR Filter design using MATLAB and Xilinx ISE in VHDL Ø Pattern recognition artificial intelligence software in C Ø PC to PC IR communication system Research interests Ø Digital VLSI design and Nano-electronic devices Achievements Ø High ranks in Highly competetive exams like IIT-JEE 2000 ( 2138 ), Roorkee 2000 (1700) , CET 2000 (45) engineering entrance exams