||Identifying the Problem
You will complete a research project that will involve the writing of two security policy, procedure and practices. Your job is to create and document two technical operations across two different areas of technology. For instance, you may choose from network, operating system, software development, application, data storage or information security. Once y...
||Nghiên cứu, An ninh máy tính, Viết kĩ thuật, Research Writing, Quản trị mạng
||Mar 12, 2018
||Mar 12, 2018Đã kết thúc
|Customize lwIP for FreeRTOS for networking swithching
||Using a FreeRTOS and lwIP (TCP/IP) on Xilinx ZynQ SoC.
Tool is Vivado 16.2 (SDK).
At Ethernet interface (PS of ZynQ FPGA), mixed traffic is to be differentiated based on pre-defined IP and Ports and IP packets are to be routed to respective application.
Rest all traffic (RAW Ethernet Frames) to be passed on to PL part (FPGA). This can be done by keeping Ethernet packets in DDR. And then AXI int...
||Lập trình C, Điện tử, Lập trình C++
||Mar 7, 2018
||Mar 7, 2018Đã kết thúc
||• Creating Layouts, Designs & Drawings and conducting analysis to identify any weakness
• Ascertaining mechanical considerations for design; applying spacing, length and differential pair constraints in design
• Building balanced stack up for impedance-controlled lines considering EMI/EMC, crosstalk analysis.
• Designed high speed interfaces such as DDR, USB, Ethernet, Sata...
||Thiết kế trang web, Thiết kế đồ họa, Thiết kế logo, Tạo thương hiệu
||Feb 20, 2018
||Feb 20, 2018Đã kết thúc
|Loan and Agent
||We are also urgently in need of an Agent in Asia, Middle East, Europe or USA With the high work volume we currently handle, we will appreciate if you can Partner with us in the area of carrying out (DDR) Due Diligence Report on our customers.
We will pay good Commission and Generous
Bonus with year end (PSC) Profit Sharing Contract. We can also provide you with up to $10 Million funds at 2%pa ...
||Feb 4, 2018
||Feb 4, 2018Đã kết thúc
|ddr sdram controller
||i want to do some modification to controller i.e either adding a module to it or pipeling it.
||Verilog / VHDL
||Jan 20, 2018
||Jan 20, 2018Đã kết thúc
|DDR SD ram controller
||DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS
Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero
||Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA
||Dec 8, 2017
||Dec 8, 2017Đã kết thúc
||Fund rasier in memory of Frankie proceeds to DDR, ( Detroit Dog Rescue)..need for Dec. 1st.
||Thiết kế Poster
||Nov 27, 2017
||Nov 27, 2017Đã kết thúc
|OpenWRT Coovachilli Project
||We have recently started working on Access points based on OpenWRT.
The access points are as below,
1. Comfast E320N
DDR: 64MB; Flash: 16MB
2. Comfast WA900
DDR: 256MB; Flash: 16MB
The current setup we have put is
1. LEDE version 17
2. Coovachilli (latest version) for controller
3. Radiusdesk (AP side)
The cloud monitoring has
||Lập trình C
||Jul 25, 2017
||Jul 25, 2017Đã kết thúc