|DDR SD ram controller
||DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS
Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero
||Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA
||Dec 8, 2017
||Dec 8, 2017Đã kết thúc
||Fund rasier in memory of Frankie proceeds to DDR, ( Detroit Dog Rescue)..need for Dec. 1st.
||Thiết kế Poster
||Nov 27, 2017
||Nov 27, 2017Đã kết thúc
|Copy a 4-layer 50x95 mm PCB (Rockchip RK3066)
||Hello, I have a PCB that I need you to copy (Gerber files), and create Altium circuitry file as well. It's a four-layer board with a Rockchip RK3066, two DDR memory chips and a bunch of other things (see the photo). Dimensions: 50x95 mm.
I have two PCBs available that I can express-mail it to your location for reverse-engineering. I need the project to be completed within 20 days or less s...
||Điện tử, Vi điều khiển, Kĩ thuật điện, PCB Layout, Thiết kế sản phẩm
||Nov 13, 2017
||Nov 13, 2017Đã kết thúc
|OpenWRT Coovachilli Project
||We have recently started working on Access points based on OpenWRT.
The access points are as below,
1. Comfast E320N
DDR: 64MB; Flash: 16MB
2. Comfast WA900
DDR: 256MB; Flash: 16MB
The current setup we have put is
1. LEDE version 17
2. Coovachilli (latest version) for controller
3. Radiusdesk (AP side)
The cloud monitoring has
||Lập trình C
||Jul 25, 2017
||Jul 25, 2017Đã kết thúc