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Dự án/Cuộc thi Mô tả Lượt đặt giá/Bài dự thi Kĩ năng Bắt đầu Kết thúc Giá (VND)
Simple Verilog code Write a simple verilog code to create dynamic lighting using led. see the attached files and respond 18 Lập trình C, Verilog / VHDL, Vi điều khiển, LabVIEW, FPGA Dec 15, 2017 Hôm nay6n 13g ₫2931818
help me with modify some Verilog code know Verilog code, how how to use Quartus and FPGA board. 9 Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, LabVIEW, FPGA Dec 15, 2017 Hôm nay6n 3g ₫590909
Create an ASIC board capable of hasing SHA256 (2-20Th/s) Good Day I am interested in finding somebody who will be able to design an ASIC board for my team and I. It needs to be able to hash SHA256 in order to mine bitcoin. It is up to you to decide whether you will be using FPGAs or other off-the-shelf ICCs. You will be working with some of the greatest experts in manufacturing and bussiness. It must meet or surpass the following specifications: ... 5 Điện tử, Vi điều khiển, Kĩ thuật điện, Thiết kế vi mạch, FPGA Dec 14, 2017 Dec 14, 20175n 19g ₫10533818182
Simulink to VHDL I have done a controller for a battery energy storage system using Matlab Simulink. I need to generate VHDL codes for my controller. If you have NOT done that, please do not wast my time. 5 Điện tử, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Dec 11, 2017 Dec 11, 20172n 10g ₫522727
simulation/ VHDL Expert Needed -- Urgent job -- b I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 7 Kĩ thuật, Điện tử, Verilog / VHDL, Kĩ thuật điện, FPGA Dec 9, 2017 Dec 9, 20173g 11t ₫1249977
simulation/ VHDL Expert Needed -- Urgent job I need a simulation/ VHDL expert for my current project. If you have knowledge please bid. Details will be shared in message with the selected freelancers. 0 Kĩ thuật, Điện tử, Verilog / VHDL, Kĩ thuật điện, FPGA Dec 9, 2017 Dec 9, 20172g 58t -
DDR SD ram controller DESIGN AND TEST OF A DDR SDRAM INTERFACE FOR FPGA SYSTEMS Integrate and generate the IP core of DDR, then configure that IP Core, with DCM, PLL, FIFO, and some memory interface with State machine, possible to show the output of writing and reading the data,. with report of Area, power and delay,. Simulation in any standard simulator , Xilinx/Actel/libero 11 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Dec 8, 2017 Dec 8, 2017Đã kết thúc ₫10159482
FPGA Implementation of FIR filter 1. FIR design and simultion in Matlab. 2. Implement in FPGA(Xilinx Virtex-6 LX240T) and inter-connect with other logic blocks. 3. define registers for FIR filter and gain setting such that user can download filter co-efficients and gain settings through software to FPGA. 24 Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Dec 7, 2017 Dec 7, 2017Đã kết thúc ₫17860540
micro controller need somebody good in micro controller and has ever coded using vhdl 18 Lập trình C, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Dec 5, 2017 Dec 5, 2017Đã kết thúc ₫3954545
Design of MIPS Datapath components Using Logisim Course: Computer Organization and Architecture Project: Design of MIPS Datapath components Using Logisim Objectives After completing this project you will: · Design a 32x 32 bit register file · Design a 32 bit arithmetic and logic unit (ALU) Register File The register file consists of 32 x 32-bit registers and has the following interface as shown in Figure 1: _ BusA and BusB... 10 Kĩ thuật, Điện tử, Verilog / VHDL, Thiết kế vi mạch, FPGA Dec 2, 2017 Dec 2, 2017Đã kết thúc ₫1022727
design and implementation of a MIPS CPU with Multi cycle Data path design and implementation of a MIPS CPU with Multi cycle Data path using the VHDL language 14 Lập trình C, Verilog / VHDL, Lập trình C++, Lắp ráp, FPGA Nov 30, 2017 Nov 30, 2017Đã kết thúc ₫3568182
bubble level project the project must be developed in verilog to be executed on the Nexys4DDR ™ FPGA Board. In the video attached in the .zip, the operation of the project 8 Verilog / VHDL, FPGA Nov 29, 2017 Nov 29, 2017Đã kết thúc ₫1886364
VHDL code for Pipe lined MIPS-RISC (5 stage) processor.(Code for Un-pipelined will be given) I need you to do pipelining for the MIPS-RISC (5 stage) Processor. I will give you the MIPS processor code, all you need to do is pipelining. I will upload the file once go through it. If you are interested, I will send you the code and question for which code has written.” Deadline is " Dec-03-2017 " 12 Lập trình C, Kĩ thuật, Verilog / VHDL, FPGA, Parallel Processing Nov 29, 2017 Nov 29, 2017Đã kết thúc ₫3909091
embedded s Project: The project consists of multiple phases. It is to develop a logic analyzer and waveform viewer (LA/WV) that can send data to a PC for display. The data collection is done on the FPGA board. A microprocessor gets data from the FPGA board and sends data to the PC through either a Bluetooth modem or a USB port. The system supports one analog channel and one digital channel, with a single... 2 FPGA Nov 28, 2017 Nov 28, 2017Đã kết thúc ₫1636364
Network traffic processing using two FPGAs I want to get throughput and latency results of network traffic(Ethernet packets processing) using two FPGAs, while i have throughput and latency results of using one FPGA, so i want to compare both these results. The results of using two FPGA chips should be better than using one FPGA. 6 Kĩ thuật, Verilog / VHDL, Kĩ thuật điện, Quản trị mạng, FPGA Nov 26, 2017 Nov 26, 2017Đã kết thúc ₫15340909
SOC integration problem About timing violation at cross clock domain 1 FPGA Nov 26, 2017 Nov 26, 2017Đã kết thúc ₫568182
System verilog - open to bidding I need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. ThanksI need a task to be completed on system verilog, please confirm if you can do. Thanks 10 Lập trình C, Verilog / VHDL, Lập trình C#, Lập trình C++, FPGA Nov 23, 2017 Nov 23, 2017Đã kết thúc ₫242043
single cycle 32bit mips verilog code -- 2 i need verilog code for 32bit mips single cycle it must contain instructions LW, SW, AND, ADD, ADDI, SUB, SLT, SLTI,b,BEQ, BNE, J, JAL and JR. and write a test-bench and stimulate and get the output waveform synthesis the code and submit to me 10 Lập trình C, Verilog / VHDL, Lập trình C++, Lắp ráp, FPGA Nov 23, 2017 Nov 23, 2017Đã kết thúc ₫227273
System Verliog task available I need someone who can do task on system verilog. Deadline is 2 days. I want someone who can start now. More details will be provided to interested freelancer 8 Kĩ thuật, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Nov 22, 2017 Nov 22, 2017Đã kết thúc ₫536582
Computer Design and ProtoTyping build a 32 bit architecture CPU, the CPU include the Register File, ALU, Control Unit, Instruction Register, Data Memory, PC Register, Shift logic unit, Conditional Logic Unit, and a 3-level cache read and write memory for the Data memory. The units need to be built in Verilog HDL then represented as a symbol on a schematic diagram and connected together using wires. Accompanied with each unit s... 8 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Nov 22, 2017 Nov 22, 2017Đã kết thúc ₫4022727
VHDL coding needed to be done by expert!! VHDL coding needed to be done by expert!! $30 CAD pay 8 Kĩ thuật, Điện tử, Verilog / VHDL, Kĩ thuật điện, FPGA Nov 22, 2017 Nov 22, 2017Đã kết thúc ₫500538
LabWindows/CVI Project Simple Update.(send emails when yields goes down) - open to bidding I need a little update in my Test Program (Labwindows). All code and GUI and all is done, just need program be capable to send email automatically to specified people when yields goes down <97%. 4 Lập trình C, Kĩ thuật, Lập trình C#, Phần mềm cài sẵn, FPGA Nov 21, 2017 Nov 21, 2017Đã kết thúc ₫3795455
UVM verification of memory controller - open to bidding Need someone to verify a memory controller using UVM environment. CAN bus is used as a memory cycle initiator and write/read burst transactions need to be verified. 5 Perl, Verilog / VHDL, Shell Script, FPGA, Very-large-scale integration (VLSI) Nov 21, 2017 Nov 21, 2017Đã kết thúc ₫8522727
SMC Interface and SPI Slave Logic for CPLD Project 1) Implement high-speed 8-bit bus for MCU (ATSAM3U) to connect to Altera CPLD (5M160ZM68C5N) 2) Implement SPI Mode-0 SPI Slave in CPLD logic 3) Implement Dual SPI Slave mode in CPLD logic 4) Implement QUAD SPI Slave mode in CPLD logic 5) Implement general purpose I/O (8-bit) Port B in CPLD logic 6) Implement JTAG Host shift logic in CPLD logic 7 Lập trình C, Điện tử, Verilog / VHDL, Vi điều khiển, FPGA Nov 21, 2017 Nov 21, 2017Đã kết thúc ₫636364
Video transmission system and USB emulator Project for huge experienced engineers. Result: Altium project and firmware. Details of the project in the attachment. 4 Điện tử, Verilog / VHDL, PCB Layout, FPGA Nov 20, 2017 Nov 20, 2017Đã kết thúc ₫32022727
Differential Scan-attack and countermeasures on AES crypto-algorithm Hi, I wanted to implement research work on the AES(Advnaced Encryption Standard) algorithm and differential scan attack on the same to retriever secret key. In addition, the prevention mechanism against such attack has to be developed. Coding and simulation in verilog(Xilinix-ISE/Modelsim) will be fine. Also, requires documents for the implementation (step-by-step procedure), block diagram ... 8 Kĩ thuật, Verilog / VHDL, Kĩ thuật điện, Mật mã, FPGA Nov 19, 2017 Nov 19, 2017Đã kết thúc ₫21481554
VHDL task URGENT Please check the attachment for the details Need to use Quartus ll 10 Kĩ thuật, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Nov 18, 2017 Nov 18, 2017Đã kết thúc ₫1022727
FPGA implementation of three phase locked loop i want to implement three phase locked loop implemented in simulink 20 Kĩ thuật, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Nov 18, 2017 Nov 18, 2017Đã kết thúc ₫11068182
FPGA and DSP develper Looking for a developer to learn and implement a real time hardware implementation of spectrum analyzer upto 100mhz bandwidth using FPGA, fast ADCs and DACs. 16 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Nov 17, 2017 Nov 17, 2017Đã kết thúc ₫1272727
implement one project with system verilog in Zynq I need to implement the threshold block and verify that with two AXI VIP as you can see in the picture. I need a testbench which generates random numbers between 500 to 1000 and the threshold block count the number of data more than 500. the project can be done also with ILA but at this point I prefer system Verilog. Xilinx has a tesbecnh example which helps to write a code quickly. 4 Verilog / VHDL, Kĩ thuật điện, FPGA Nov 9, 2017 Nov 9, 2017Đã kết thúc ₫2162226
vhdl code using xilinx vhdl code using xilinx and simulate it using isim 14.7 7 Kĩ thuật, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Nov 7, 2017 Nov 7, 2017Đã kết thúc ₫727273
embedded systems Modify the previous assignment so that, a bit string of 16 bits is sent from the UNO to the FPGA using a single data wire plus one or two control wires for synchronization (which could be either strobing or handshaking). When a pushbutton on the FPGA board is depressed and released, the FPGA sends a bit string of 16 bits to the UNO for display. Depending on the XOR result on the 16 bits, the ... 12 Verilog / VHDL, Kĩ thuật điện, FPGA Nov 7, 2017 Nov 7, 2017Đã kết thúc ₫4204545
FPGA Project Detail will be given in contact. 19 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Nov 7, 2017 Nov 7, 2017Đã kết thúc ₫3931818
KC705 and SD Card I want VHDL implementation of data saving to SD card and reading it back when necessary. Main deliverables are: 1. VHDL Code using KC705 Evaluation kit. Detailed commenting must be there inside code to better understand the code. 2. Complete documentation of the code so that it can be enhanced in future. 3. Examples on how to use the code to write or read. 4. Detailed information on interface ... 2 Điện tử, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Nov 3, 2017 Nov 3, 2017Đã kết thúc ₫613636
Project for Pradeep S. Hi Pradeep S., I noticed your profile and would like to offer you my project. We can discuss any details over chat. 3 Python, Vi điều khiển, , Arduino, FPGA, Raspberry Pi Nov 1, 2017 Nov 1, 2017Đã kết thúc ₫363636
Verification IP development for AXI Protocol using system Verilog VIP component development for AXI3.0 protocol with support for various features like burst type, burst size, protection, out of order, overlapping, aligned,WRAP,fixed burst . Develop BFM, Generator, Monitor, and Coverage models and also the slave model. 5 Lập trình C, Verilog / VHDL, Kiến trúc phần mềm, Lập trình C++, FPGA Oct 31, 2017 Oct 31, 2017Đã kết thúc ₫3929856
Electrocardiomiografo Integración de electrocardiografo y electromiografo haciendo uso de una FPGA para filtrado digital, procesamiento de datos y envío de información por medio de HC06 al celular. 9 Verilog / VHDL, Kiến trúc phần mềm, Thiết kế vi mạch, FPGA Oct 30, 2017 Oct 30, 2017Đã kết thúc ₫1204545
Video product reviews We are a software company in the EDA industry. Our users are FPGA or ASIC engineers working in VHDL and/or SystemVerilog. We are looking for several people to create and distribute online video content for us on a regular basis. What skills do you need? - knowledge on hardware design projects - coding in VHDL and/or SystemVerilog - professional verbal and written English How can you ... 6 Điện tử, Dịch vụ video, Verilog / VHDL, FPGA, Editorial Writing Oct 30, 2017 Oct 30, 2017Đã kết thúc ₫4181818
VHDL Coding VHDL Coding Project. Knowledge of Micro electronics is needed 12 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Oct 27, 2017 Oct 27, 2017Đã kết thúc ₫181818
Digital system and microprocessor small task -- 2 small task on digital system and microprocessor using verilog amount usd 20 time 1 day 16 Điện tử, Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, FPGA Oct 22, 2017 Oct 22, 2017Đã kết thúc ₫659091
Digital design using Verilog Use Basys 3 Board and Vivado 2016.2 I'll share the rest details 7 Verilog / VHDL, Vi điều khiển, Kĩ thuật điện, LabVIEW, FPGA Oct 20, 2017 Oct 20, 2017Đã kết thúc ₫954545
verilog project making verilog on quartus II (cyclone IV) 12 Kĩ thuật, Verilog / VHDL, Kiến trúc phần mềm, Lắp ráp, FPGA Oct 18, 2017 Oct 18, 2017Đã kết thúc ₫3340909
veriloghdl code for calculation area THis must implement on quartus( altera FPGA cyclone IV) 3 Lập trình C, Verilog / VHDL, Vi điều khiển, Lập trình C++, FPGA Oct 16, 2017 Oct 16, 2017Đã kết thúc ₫2909091
Simple Verilog Project Design a perception timer that measures the time for a user to respond to a request to complete a simple task. I'll send the rest details for part 3. 8 Kĩ thuật, Matlab and Mathematica, Verilog / VHDL, Kĩ thuật điện, FPGA Oct 13, 2017 Oct 13, 2017Đã kết thúc ₫545455
Color space conversions and FPGA's 3 pages report in two parts on: (i) fundamental information about FPGAs and their programming, and (ii) standard color spaces and formulas for converting those color spaces into other ones. (Plagarism free) finished in 3 days maximum. 9 Kĩ thuật, Verilog / VHDL, Kĩ thuật điện, FPGA Oct 13, 2017 Oct 13, 2017Đã kết thúc ₫1500000
VLSI PROJECTS FIND THE ATTACHED IEEE [url removed, login to view] REQUIREMENTS 4 Verilog / VHDL, FPGA, Very-large-scale integration (VLSI) Oct 11, 2017 Oct 11, 2017Đã kết thúc ₫1950058
Linux, Kĩ thuật điện, Ubuntu, Debian, FPGA Oct 10, 2017 Oct 10, 2017Đã kết thúc
Metatrader, PLC & SCADA, Phân tích phần tử hữu hạn, Thị trường thương mại, FPGA Oct 10, 2017 Oct 10, 2017Đã kết thúc
Assemble and calibrate audio amplifier Hello i am working in audio and develop a high end audio loudspeaker to power this loudspeaker i have chosen pcb amplifier i need a skilled person to get the whole working 1/ indicate me the power supply to use ( toroïdal) 2/do all the wiring (i provide the switch) 3/assemble the pcb board, toroidal transformer .... switch... it will happen in your city i already have switch... 6 Dịch vụ audio, Vi điều khiển, PCB Layout, Thiết kế vi mạch, FPGA Oct 8, 2017 Oct 8, 2017Đã kết thúc ₫4975869
STM32 motor control project template Hey guys, I started using STM32 motor workbench and FOC SDK v4.3, and the code is a bit more complex than what I'm used to. For that reason, I need someone experienced in STM32 FOC library, to create some functions that are easier to use for a part time coder. Project description as follows The target of this project is to design a template using STM32 FOC SDK v4.3. This template shall h... 12 Vi điều khiển, PLC & SCADA, Arduino, Thiết kế vi mạch, FPGA Oct 8, 2017 Oct 8, 2017Đã kết thúc ₫14184116
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