Fpga e1 framercông việc

We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

You will develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created ...“logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minim...

You will develop a CAD tool that can read in the “logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created ...“logical RAMs” in each circuit of a benchmark set, and output a set of “physical RAMs” that can implement the logical RAMs for each circuit. Your tool should be able to target FPGAs with up to 3 types of physical RAMs (which may be 3 different block RAMs, or 2 block RAMs and “LUTRAM” created by using a logic block as RAM). Your CAD tool should attempt to find a solution that minim...

I need a flyer designed in 24 hrs please ensure its of a nice size to post on social media especially instagram. details to include: Saturday 10th November 2018 at Track & Records 94 Middlesex St, London E1 7EZ Music Policy: RnB, Hip Hop, Dancehall, Reggae, Trap, Afrobeats, Garage & House Use T&R maybe as background Image or use the image in there some where. use my attachments in the flyer also get an instagram twitter and soundcloud image and put follow @djslenderuk thank you

I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit...chasing you and if he catches you, you are dead. The player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have lots of comments, documentation, and test (.do) files so that it can be easily understood by a beginner. This should fully be implementable with the Cyclone 5 ters...

Working on a first prototype version of our Digital Real Estate Managment Assistant, we need some help on certain transactions a feature to build within our Framer X prototype. Therefore we are looking for a REACT developer familiar with the capabilities of Framer X to support us. We would consider an arrangement about 1 - 3 months one day a week. Requirements: - Knowing Framer X or keen to learn it - Min. 2-year experience of REACT development - Communicative in terms of active reporting - Familiar with Scrum Methodology using Asana, Jira, Github or keen to learn it - Fluently in English, as we will hold Skype meetings once a week - a holistic understanding of the possibilities within web development (nice to have) - python would be nice but nur necessary Most imp...

I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made -- not imported from a library etc. The ...quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made -- not imported from a library etc. The work should have lots of comments ,documentation and test (.do) files so that it can be easily understood by a beginner. it should work with a FPGA...

I need an FPGA selected and hardware design created for decoding of an MPEG-Transport Stream parallel interface from a DVB-T demodulator. The FPGA needs to decode the transport stream and extract the video data as well as any other data contained in the Transport stream, the FPGA must then extract a selected individual pixel, and its colours are extracted in 8 bit form (8bits for each of RGB). This pixel data will be outputted to an LED. The FPGA will know which pixel to select after decoding the transport stream and receiving data from the transport stream to tell it which pixel to select.

Hey Guys, My Project description is given below. Please rea...Project description is given below. Please read carefully and if you already have this you can modify that but I need the code running on FPGA board after I download it to it. Description: You have to create the VHDL model for the 4-bit multiplier. You must also synthesize the VHDL model, download to FPGA and test your multiplier on the FPGA board. Use a push button on the DE10-Lite FPGA to provide the clk input to the multiplier. The A, B, Start and Reset inputs should be controlled by toggle switches on the DE10-Lite board. You must display the Done output on an LED and the result (product) as a three-digit decimal value on three seven segment displays on the FPGA board. You also need to sh...

I need help with Sketchup. I need someone to be able to add the framer plug in to my file and also be able to come up with a list of materials needed for the construction project.

This is a multi-part project for the Lattice MACHXO2-4000 LOGIC IC.

Looking for a developer to interface high speed TI DAC with virtex 7 FPGA. I am having DAC34H84 DAC and VC707 kit- and want to interface the same DAC with VC707 Hardware that i have is DAC34H84 and VC707

- schematic capturing; - PCB lay-outing; - production files generation, prototype bringing-up and troubleshooting; - transferring to production. Required experience: mixed circuitry hardware design, digital interfaces: USB, ADC (120MHz), analog circuitry: impedance matching, ADC, frequencies up to 100MHz, clocking and sync schemes, FPGA/MCU and peripherals. Job Type: Contract Location: GTA

A simple boundary extraction project that involves eroding a binary image using morphological structuring element, and subtracting the outcome from the binary image to get boundaries.

We are a Signal processing Company, we are looking for designing a Board which can take 2 Channels of 70 MHz Input, 2 Channels of Baseband Signal 10 MHz BW, 2 Digital TTL Channels with 10 MHz Rate and Ethernet Port for data transfer. All the Inputs and Outputs have to be connected to an FPGA processor Zync.

...for one freelancer to develop FPGA software for best mining algo using Xilinx FPGA VCU1525 card. You will have to program an FPGA card that I will provide, to work for crypto mining. Is necessary also customize mining software that works under Windows to by able to works with the FPGA. Software must have to be perfectly optimized. You will work in our office in our country in Europe or you can work remotely if you have necessary equipment. We'll provide food and accommodation. You will be hired with a regular working contract with NDA. Deadline to complete the programming is 30. So you MUST be expert at programming FPGAs. You will get paid at the END of the job once successfully accomplished. Possibility of permanent cooperation for us. We are askin...

* Full Instructions found in pdf attachment. File: System_Verilog_Instructions * * Sample Code is found in attached files * * Program used : Quartus Prime * * Block Diagram template also found in attached files * * Hardware used: DE10-Lite kit with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the work done and how they link together. I will program my hardware with what is given. Thank you in advance.

1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

Hi ! I currently need pcb layout engineer to upgrade my personal fpga board. It previously used Spartan 3E FPGA PQFP (PQ208/PQG208) package using the power voltage of 3.3v, 2.5v, 1.2v ... I'd like to have it replaced by an Artix fpga (FG484/FGG484 Fine-Pitch BGA package), henceforth using the lower voltages of 3.3v, 1.8v, 1.0v The voltage regulators are in SOT-223-3. There are some new components too... There are all the links to other parts of the circuit to be re-layout. The work must be done in Altium Designer.

I would like to port Nueral network for image identification on PYNQ FPGA

more details will be given in the chat and it more of writing article on this, if you cant write article on this please dont place your bid

The goal is to design a game on Xilinx FPGA. More details on chat. The deadline will be 3 days. Only serious bidders who can complete in 3 days should bid. No Excuses. Time wasters avoid bidding, please.

Cryptocurrency Mining Application in C or C++ We are seeking a senior engineer/architect with experience working with cryptocurrency mining systems to provide technical consultation and to implement (or guide implementation) of a mining application for an FPGA via MicroBlaze.

FPGA, Embedded system writing and classification.

I need someone to help me repair this COUNTIF formula =IF(COUNTIF($E$1:$E$13300,E1)=1,"Unique",COUNTIF($E$1:$E$13300,E1)) Here also is a video which shows the difficulty that I am experiencing. Assistance is greatly appreciated. I will pay $4 for full completion of this task. The solution must work in my existing sheet.

Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

Hi Ahmed M., I noticed your profile and would like to offer you my project. We can discuss any details over chat. It's about a Basys 3 FPGA control of an LCD, LED of the boards, a encoder and a ultrasonic sensor. please let me know if you can finish it in less than 2 days and in budget and we can discuss it

I'm looking for an experienced SERDES engineer to design a SERDES PCS on ASIC. This PCS will be connected to a PHY(PMA) IP, encoding the data with 8b10 protocol and then transmitting (no receiving) the data out through the PMA, 5Gbps. The data will be received by a Xilinx FPGA GTH Transceiver and then decoded. Therefore the PCS logics shall be compatible with the GTH Transceiver. Your tasks are 1. Write the PCS RTL code 2. Provide a compatible GTH transceiver configuration/RTL. 3. Provide guidance on verification of the whole link channel.

Design and development of non-invasive medical electronics devices that support and aid medical professionals in data acquisition and communication with expertise on processor/operating system/testing/system validation, FPGA design, integration of medical sensors, porting, middleware and application development.

Hi Loi L., I noticed your profile and would like to offer you my project. =================== The details : - my profile : fpga hobbyist newbie / singapore / currently working in a non-technology industry - hardware : - board : DE10-Lite MAX10 10M50DAF484C7G - monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux Mint). - language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output image to monitor - issue : the above seems to work fine, *except* th...

i have attached the document below. And i need this on 21st of october.

...challenging requirements in signal processing. We are developing a transmitter with digital modulation schemes with shorter delivery time. We developed all the algorithms required in LabVIEW FPGA. The same have to be ported to VHDL and be integrated before programming the Xilinx V6 FPGA on the transmitter. Complete hardware and many of the software blocks in VHDL are already built by our team. The requirement is urgent. Entire work to be completed in 2 - 3 weeks. Any freelancer with experience in integrating system level codes in VHDL, basics of digital signal processing and programming Xilinx Virtex-6 FPGA would better fit our requirement. Before hiring, initial discussion with Freelancer is essential to understand the his/her experience and to detail the sco...

Need an expert in xilinx vivado Projects are based on digital systems on topics such as Multiplexers Flip flops registers Counters Clock dividers Please contact for project instructions and further details

I have my working model of neural network. I want to develop an accelerator on FPGA and show improvement in power.

...professional can bring a new level of exposure to your business. Just one sentence. Context is the advantage of hiring a professional for that certain skill. Jenkins Keras Pytorch Firmware Visual Merchandising Mobile App Testing Video Production Landscape Design Online Writing Financial Analysis Drafting Package Design User Experience Design Moving Swift Autodesk Inventor Tattoo Design Call Center FPGA Handyman Microsoft SQL Server Digital Marketing Wikipedia Zbrush Carpentry Book Artist Procurement Database Development Raspberry Pi Wix VB.NET Sketching Email Developer Network Administration Excel Macros Email Handling Filmmaking 3D Model Maker VMware PEGA PRPC Business Writing General Labor Plumbing Geographical Information System (GIS) PPC Marketing Full Stack Development J...

I have a matrix with rows being the combinations and columns being the players. I want to compare the combinations for example [A1,B1,C1,D1,E1] & [A2,B1,C1,D1,E1]&[A3,B1,C1,D1,E1]&[A4,B1,C1,D1,E1] in short I need to find the greater value between A1,A2,A3,A4.

We are looking for someone who is very good with high speed digital layouts. The application is an Ethernet to digital audio motherboard. A daughter card with an Zynq FPGA/processor will install on this motherboard, and the motherboard will install onto a DAC board. There is a development board for this daughter card already. So this motherboard will just be a stripped down version of the development board with only the features we need. And powered by different regulation. If this sounds like something you'd be good at please let us know.

I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data for later use ( average, mean,... etc).

I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

I want to build an app that likes Ohana and Gtruck app Here is the link: Deadline: 1 month

I need someone to modify the ccminer software. So it can communicate with FPGAs instead GPUs. It needs to work with both usb and pcie. I'm not asking for algorithm programming, I'm not asking for bitstreams. Just modifying the mining app ccminer so it works with FPGAs.

Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

I'm looking for someone to design a mobile app that will ultimately be developed for use on iOS an...that will ultimately be developed for use on iOS and Android. I am not looking for development at this time... just the UI Design. In short, the mobile app allows users to record, save and organize audio messages. The audio messages can then be shared with one or more users on the platform. I expect this app will consist of 10-15 screens. I would like for you to use either Invision Studio OR Framer when designing the app... starting with wireframes and then, once approved, complete the graphical UI. The design should be responsive and scalable from mobile phones to tablets. Please provide a link to your portfolio... and feel free to comment on any related projects that you ...

coding of bitstreams, software licensing, imbedded commission

Hi All, I have a project for someone who is expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse the captured signal. 4- The processed signal should then be accessible on a website (Fig. 3) 5- For part 4 LabVIEW NGX web Module may need to be used. Note 1: ******You MUST have MyRIO****** Note 2: I am not looking for dashboard or something else. Note 3: The currency is in the Australian dollar. Please do not bid if you have not read the above proposal. Regards, Keano

Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

Hi All, I have a project for someone who is expert in using MyRIO, MyRIO FPGA and MyRIO web services (Fig1 and 2). The project steps are explained as below: 1- The MyRIO should capture a signal (can be anything) with the sampling frequency of 5KHz. 2- Eleven (11) seconds of the signal must be captured. 3- I will provide you with two (2) MATLAB codes that must be run by MyRIO FPGA to analyse the captured signal. 4- The processed signal should then be accessible on a website (Fig. 3) 5- For part 4 LabVIEW NGX web Module may need to be used. Note 1: ******You MUST have MyRIO****** Note 2: I am not looking for dashboard or something else. Note 3: The currency is in the Australian dollar. Please do not bid if you have not read the above proposal. Regards, Keano

Good evening, I'm trying to make a project but I haven't purchased a board yet because I'm not sure which board to buy. So far, I've looked at the Zybo-Z7 or Arty-Z7. You will need to have these boards already obviously to complete this project. They both have sample projects for HDMI in and HDMI out. What I'm trying to accomplish is have: 1) PC->HDMI->FPGA->HDMI->Monitor 2) PC->USB-> FPGA 3) The PC will send information to the FPGA and create an overlay on the monitor. This software on the PC could be coded in C++ or C. Example, DrawText(x, y, "Truck #19 ready for shipment.") There are many samples online but my knowledge is too limited to combine USB communication and Drawtext or shapes over the income HDMI fee...

We are looking for DSP Firmware Engineer who has specialized in algorithms' performance optimization for DSP/FPGA based on VLIW architecture.