verilog pragramming - open to bidding

1 • Development of a hardware description for a parameterizable signal generation. • The waveform is to be realized by biphasic constant current pulses which are to be varied in duration and amplitude. • The signal generator is to stimulate up to four independent electrodes in a time-multiplexed process with stimulation patterns. • The entire system must be validated by creating testbenches and simulations. • The Xilinx ISE environment is used for development and test purposes. 2 • Development of a hardware description for a data interface. • A suitable data protocol and an interface concept must be developed that meet all requirements with a low number of lines. • The data interface should be cascadable, comparable to a daisy chain. • The data interface should be able to describe both the configuration registers and the stimulation data in the EEPROM of the ASIC. • The entire system must be validated by creating testbenches and simulations. • The Xilinx ISE environment is used for development and test purposes